Research And Design Of Key Circuits In 14-bit High-speed Pipeline ADC

Analog-to-digital converter(ADC)is located at the front of signal processing chain.It acts as a bridge between Analog domain and Digital domain.Its performance is very important for the whole signal processing system.Different application fields have different requirements for ADC precision and speed,so different types of ADC architectures are derived.With the advantages of both speed and precision,pipeline ADC has become a popular choice for high-speed and high-precision ADC research.It is widely used in multimode multifrequency high-speed digital receivers,3G/4G/5G and other high-speed wireless communication systems,phased array radar systems,high-speed broadband electronic measuring instruments and other applications.The key circuits in high-speed pipeline ADC are the focus of this thesis.Based on the description of pipeline ADC architecture and operational principle,the functions of sample-and-hold circuit,MDAC unit and sub-ADC circuit are analyzed.Meanwhile,the structure of MDAC module,redundancy correction technology and existing error sources such as limited gain and limited bandwidth are analyzed.A 14-bit high-speed pipeline ADC is designed in 40 nm CMOS technology in this thesis.The system consists of six 2.5-bit pipeline stages and at last a 2-bit flash sub-ADC.Each stage adopts redundancy correction technology to reduce the influence of comparator offset and other factors on the circuit.In the sample-and-hold circuit,the switch-bootstrapping technique is used to improve the linearity of the switch.A high-speed dynamic comparator is used in the sub-ADC to improve the comparison speed.The operational amplifier uses 2.5V power to solve the problem of limited output swing,and uses gain-boosting technique and Ahuja frequency compensation technique to improve the performance of operational amplifier in gain,bandwidth and stability.The core layout of the 14-bit pipeline ADC designed in this thesis is 780μm×300μm,and the power consumption of the whole circuit is about 430 m W.The post simulation results show that when the sampling frequency is 500 MHz and the input signal frequency is about 250 MHz,the effective number of bits of ADC is 11.10-bit and spurious free dynamic range is 75.68 dB,which meets the design requirements.