The Research And Design Of 10-Bit 40MHz Pipelined ADC

As one of the most difficult chips in thousands of chips,Analog to Digital Converter(ADC)has been the core problem that has plagued the country's development of integrated circuits.With the development of wireless communication technology,the 5G era is about to Coming soon,making a 5G chip,or having a mature ADC chip that can be applied to a 5G chip,is a top priority,and it also places high demands on the accuracy,power consumption and area of the ADC.Pipelined ADCs can maintain a good modest performance in terms of performance involved.For this purpose,this article will focus on pipelined ADCs.In this paper,the key modules of the pipelined ADC are designed and designed.The principle and error source of the working module in the pipelined ADC are analyzed.On this basis,the SMIC 40 nm process is used for the full-differential operation of the gate-voltage bootstrap switching circuit and the pipelined ADC circuit.Design and simulation of key module circuits such as amplifiers,comparators and non-overlapping clock circuits,and finally completed the overall ADC design simulation and layout design.details as follows:(1)Designed a gate-voltage bootstrap switching circuit,which can effectively improve the linearity problem caused by the secondary effect of the sampling switch,and improve the linearity of the sampling switch by using the substrate technology,thereby improving the ADC.Precision.(2)Designed a sleeve-type fully differential operational amplifier used in the sampling switch,using a two-stage common-mode feedback circuit to improve the common-mode feedback problem in the operational amplifier,with greater DC gain and Output swing,better stability,and its gain,phase margin,bandwidth and other indicators have also met the requirements.(3)Design a dynamic comparator used in the digital converter of the sub-converter(dac)to improve the one-bit output of the traditional comparator and add one output to make the quantization result more accurate.(4)The design completes the bias circuit,and the two phases do not overlap the auxiliary circuit such as the clock circuit and the delay circuit.In this paper,the module design of the sub-converter of the pipelined ADC is completed.Based on this,the structure of the entire 10-bit 40 MHz pipeline ADC is designed.The simulation results show that the signal amplitude AMP is-1.56 dB,the signal-to-noise ratio SNR is 60.28 dB,the signal-to-noise distortion ratio is 54.72 dB,the spurious-free dynamic range SFDR is 74.83 dB,and the total harmonic distortion THD is-67.13 dB.The nonlinear DNL range is-0.26~0.36 LSB,and the integral nonlinear INL range is-0.66~0.67 LSB.And the layout is designed for each module circuit,and the overall layout design is finally completed.