Research And Design Of High Speed Pipeline ADC

With the development of semiconductor preparation technology,digital information processing technology has been rapidly developed,digital circuit in signal processing is more stable and fast;However,in the real world,most signals exist in the form of Analog signals,which cannot be directly recognized by the Digital system.As an Analog to Digital Convertor(ADC),analog signals in the real world can be converted into digital signals that can be processed by the digital system.The speed,precision and power consumption are required to be higher.Thesis based on the consideration of ADC speed,accuracy and power consumption,a high speed Pipeline ADC consisting of a sample-hold circuit,a pipeline-level 10-level significant bit 1 with 0.5 redundancy bit and a 2-bit fully parallel ADC(Flash ADC)structure is proposed.Based on this,a 12-bit Pipeline ADC with a sampling frequency of 100 MHz is designed.Based on the chip performance,i In order to obtain higher accuracy and speed and achieve the purpose of reducing power consumption,a capacitor flip sampling and holding circuit and a capacitor flip gain digital analog unit(MDAC)are designed.The pipeline level significant digit is designed as 1 bit and 0.5 is added as a redundant bit to increase the tolerance of the system to the offset voltage of the comparator.The dynamic latch comparator,which is faster and has no static power consumption,is used as the comparator module in this design,which further reduces the power consumption of the chip.Finally,according to the high requirements of the architecture for operational amplifiers,a gain bootstrap folding common-source common-gate operational amplifier with 116 d B DC gain bandwidth 870 MHz and phase margin 77°is designed.Finally,Based on SMIC 180 nm 1.8 V standard CMOS hybrid technology,the circuit schematic and layout were designed using Cadence Spectre software.The core layout area was 1408 μm × 808 μm.The simulation results show that when the sampling rate is 100 MHz and the input signal frequency is 6.05 MHz,the ADC has a spury-free dynamic range(SFDR)of 82.47 d B,a signal-to-noise distortion ratio(SNR)of 71.90 d B,and a significant bit(ENOB)of 11.65 bit.The power consumption is 80 m W at the supply voltage of 1.8 V,and the Figure of Merit factor(FOM)is 248.93 f J/conversion-step.The simulation results show that this structure can achieve a compromise of high speed pipeline ADC performance.