Research And Design Of Low-power Pipelined Adc

With the explosive growth of wireless communication systems and portable consumer electronics, the demand for low-power and small size analog-to-digital converters (ADC) and other mixed-signal circuits becomes indispensible. Among various medium-resolution analog-to-digital converter architectures, pipeline ADC is considered for achieving a good tradeoff between speed, power consumption and chip area.In this thesis, a 10-bit 100-MS/s pipeline ADC is constructed which consists of eight stages with 1.5-bit/stage architecture, except for the last stage which is a 2-bit Flash ADC. By applying 1.5-bit/stage architecture and digital error correction logic, the accuracy of Sub-ADC in each pipelined stage is reduced. Therefore, dynamic comparators with no dc power dissipation can be used to implement the Sub-ADC. Besides that the sampling capacitors and operational amplifiers are scaled down along pipelined stages, in order to further reduce power consumption and chip area, another two circuit design techniques are used to implement pipeline ADC in the thesis. Specific design techniques include:(1) First pipeline stage design technique without using a conventional front-end sample-and-hold amplifier (SHA), which also improves the dynamic characteristic of ADC, due to avoiding the noise and nonlinearity introduced by SHA itself.(2) Dual input pairs switched operational amplifier sharing technique, which eliminates both the need of additional series switches for sharing the input pair, and memory effect introduced by the un-reset input pair of conventional operational amplifier.A low-voltage, low-power 10-bit 100-MS/s pipeline ADC is designed in a 0.18-μm CMOS (only CMOS devices in the BiCMOS process are used) process. The designed ADC achieved 73.23 dB SFDR and 59.67 dB SNDR for a Nyquist input (48.85 MHz) at full sampling rate from Transient Noise simulation, while consuming 19.7-mW from a 1.8-V supply.