| High-speed and high-precision analog-to-digital converters are widely used in wireless communications,data acquisition,optical communications,instruments and other fields,and are the key link in the transformation of analog systems to digital systems.Whether in the national defense industry or civilian use,the demand for high-performance ADCs is increasing day by day,but there are very few localized chips.A comprehensive study of the research results of high-speed and highprecision ADC chips at home and abroad in recent years shows that the pipeline ADC adopts a hierarchical structure,which has the advantages of high resolution,fast sampling speed,and reproducible circuit structure.Therefore,this paper adopts the pipeline ADC to realize the analog-todigital converter with 12-bit resolution and 1GS/s sampling rate,which has a wide application prospect.The pipeline ADC designed in this paper adopts a 6-stage pipeline structure of 2bit+3bit*4+3bit.The key circuit modules include non-overlapping clocks,high-speed dynamic comparators,highperformance differential op amps,bandgap reference sources,and reference voltage generation circuits.Wait.By comparing and analyzing the clock circuit based on the charge pump and the clock circuit based on the delay locked loop,the delay locked loop structure with less clock edge jitter is selected to realize the clock circuit.Based on the strongarm structure of the high-speed dynamic comparator,the design of cross-coupling input is introduced to realize the full swing input range and meet the system design requirements.By optimizing the sample-hold circuit structure and adopting a distributed design,the overall power consumption is greatly reduced.In order to meet the accurate closed-loop amplification,a sleeve-type cascode operational amplifier circuit with a gain boosting structure is used to achieve the system design index.The simple combination of pipeline-level digital outputs is improved,and redundancy correction is performed on the outputs of the first five stages to eliminate bit errors caused by signal overflow.Based on the 40 nm CMOS process,this paper has completed the circuit and layout design of the12 bit 1GSPS pipeline ADC,and the overall layout area is 1173μm×576μm.The simulation results show that the temperature coefficient of the bandgap reference circuit is 2.86 PPM/℃,and the openloop gain of the operational amplifier circuit reaches 84.7d B.When the input signal frequency is50 MHz,the ENOB of the ADC reaches 10.27 bit,and the SNDR reaches 63.58 dB. |
