Design And Implementation Of A 12bits 100MSPS Pipeline ADC

High-speed, high-performance, analog-to-digital converters (ADCs) are the important building blocks in many applications. Various architectures such as folding architecture, folding and interpolating architecture, sub-ranging architecture and pipeline architecture have been used to implement high-speed, high performance ADCs. In all of these architectures, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems, especially, for applications requiring portability where power dissipation is a primary concern.In this work, a 12 bits, 100Msps, low-voltage, high-performance pipeline ADC is designed and realized in deep submicron 0.18μm CMOS technology. The main content of this works includes as follow.1. Various ADC architectures and their characteristics are investigated and compared, the pipeline architecture is determinated to be used in this project.2. The non-idealities of the circuit are carefully investigated in order to identify the circuit requirements for the pipeline ADC. The resolution per stage plays an important role in determining the performance of the pipeline ADC. A behavioral model of this ADC is realized by the Simulink of Matlab in order to trade off the complexity of the entire circuit and the resolution of the stage. A system level model is used to determine the requirements of the gain of interstage and the DC gain, unity-gain bandwidth and other parameters in every stage.3. A deep investigation is made in the most important modules such as sample and hold, 3.5Bit MDAC, 1.5Bit MDAC in Pipeline ADC. In order to enhance the linearity and the bandwidth of the sample and hold circuit, a bootstrapped switch is designed. A gain-boosting folded-cascode op amp is elaborately realized and can meet the requirement of the precision of the Pipeline ADC. Flip-around architecture is adopted in multiplying DAC to enhance the speed. According the requirements determinated by system-level model of pipeline ADC, the circuit is designed, the simulation is carried out, and the layout of the circuit is implemented for all the modules in the pipeline ADC.4. A 12 bits 100Msps Pipeline ADC is designed in 0.18μm digital CMOS process. The area of ADC is 3538μm x 1699μm, the common mode voltage of input and output is 0.8V, the swing of the input and output is larger than 1V, and the power dissipation is 823mW at 1.8V power supply...