12-bit High-speed Pipeline ADC Design

As the front-end core device of the digital signal processing system,the analog-to-digital converter(ADC)is a bridge connecting the analog world and the digital world.With the development of wireless communication technology and CMOS process technology,ADCs are also moving toward high speed and high resolution.In many ADC structures,the pipeline structure has a good compromise among speed,resolution,area and power consumption,and thus is the mainstream architecture of high-speed and high-resolution ADC research.In this dissertation,a 12-bit high-speed pipeline ADC is designed using 40nm CMOS technology.Firstly,the basic working principle of the pipeline ADC and the corresponding time sequence are introduced.And then in-depth research and analysis on various non-ideal factors affecting high-speed and high-resolution ADC are conducted.Based on these theoretical studies,the SHA-less architecture and the combination of 2+3+3+3+3+3 pipeline level conversion are adopted in the design of 12-bit high-speed pipeline ADC.Besides,stage scaling-down technique is also adopted in the design.In order to reduce the influence of non-ideal factors such as comparator offset voltage,digital redundancy technology is used in pipeline stage.Due to the low-scale process node and the low supply voltage limit for high-gain and wide-band operational amplifiers,two-stage miller-compensated operational amplifier is designed to ensure the high-speed pipeline ADC's demand for operational amplifier bandwidth.For the inter-stage gain error caused by insufficient operational amplifier gain and capacitance mismatch,the auxiliary calibration technique is used in the design.The calibration measures the error in the digital domain and designs a programmable feedback capacitor circuit to calibrate the gain error.The simulation results show that the maximum differential voltage can be input by the 12-bit high-speed pipeline ADC is 1.4V at 1.1V power supply voltage.At 300MHz sampling frequency,an ENOB of 10.74 bit and an SFDR of 70.83 dB are available.The total power consumption of the circuit is about104mW and the core area is about 0.18 mm~2.