System Modeling And Key Circuits Design Of 25Gb/s CDR

With the rapid development of information transmission,the transmission rate of parallel communication technology is limited due to some non-ideal factors.Serial communication technology gradually replaces parallel communication technology and becomes the mainstream scheme of communication technology research and development in recent years.In order to solve the problem of signal attenuation and distortion caused by signal transmission,the clock data recovery circuit(CDR)which can recover low jitter and high quality is needed in the optical communication system.the role of the CDR is samples from the received data and extract the certain cycle of synchronous clock,provide some subsequent module circuit synchronous clock signal,and then through the clock signal extracted by drive decision circuit receives the data flow in timing,reduce the jitter in the process of data transmission,eye diagram more clearly higher quality of high-speed serial data stream.This paper studies and designs a PLL based full rate 25Gb/s linear CDR circuit without external reference.The CDR structure mainly includes mixing linear phase detector(PD),automatic frequency detector(FD),voltage and current converter(V/I),low pass filter(LF),LC voltage controlled oscillator(VCO),buffer circuit(BUFFER)and retiming circuit(Retiming)and other key module circuit.The purpose of CDR designed in this paper is to improve the speed of linear CDR to 25Gb/s under the condition of low jitter and low power consumption.On the basis of theory,this paper analyzes several typical common CDR structures in detail,and describes several key performance indicators of CDR,including speed,jitter and eye diagram,and then puts forward the specific structure and design process of 25Gb/s CDR.Matlab Simulink was used to model the 25Gb/s CDR system and verify the feasibility of its loop.In this paper,a mixed-frequency linear PD is designed to solve the problems ofHogge PD’s limited speed and Alexander PD’s large jitter.A reference pulse with fixed phase difference is generated by phase detection of the delay data and the input data.Then,an XOR is used as a mixer to mix the reference signal with the clock signal to ensure that the loop has a large enough passband to achieve high-speed operation.Generates an output pulse whose width is proportional to the phase difference between the input signal and the clock signal when the pulse edge is present.An automatic frequency detector is used in this paper,the FD not lock automatically activated in loop circuit,the frequency acquisition is completed automatically closed loop,don’t need to lock detection module,this can make hardware and minimize power consumption,and this kind of non-reference frequency detector uses the delay data V_Band V_D generated by the PD delay circuit.It does not need additional orthogonal clock,the design of FD is simplified and the power consumption is reduced.In this paper,the circuit design,layout design and pre-simulation analysis of 25Gb/sCDR are carried out by using TSMC 65nm CMOS technology.The simulation results show that the power supply voltage of 1.2 V,27 degrees,typical process Angle,CDR clock jitter 1.9857 ps,data jitter 2.9547 ps,rising/falling edge is less than 16 ps,power consumption is 112.5 m W,bandwidth is 40 MHz.CDR chip area is2026.12μmí1363.72μm.Reach the target.