Clock Recovery In High-speed Serial Communication Technology

Serial link technique is the main method used for backbone data communication. The clock recovery circuit (CDR) is the important building block for the receiver, whose performance decides the overall receiver performance.Several factors affect the signal characteristics at the receiver end. The media attenuates the high-speed data, and bring on inter-symbolic interference and results in input jitter for receiver. The function of CDR is to extract the clock from the jittering data, which needs to find out the optimum sampling point. Closed-loop CDR is based on the principle of phase-locked loop, and it has good characteristics in jitter tolerance and attenuation, which is suitable for high-speed serial link.Different serial link applications have different performance requirements for the CDR. Building block choosing and performance optimization is made accordingly. The dynamic characteristics of CDR include input jitter tolerance, jitter output and lock-in speed, which are strongly related to the loop characteristics. Non-linear phase detector introduces difficulties for loop linear analysis. To solve this problem, one method is linear approaching using small signal, the other method is behavior modeling, which is more close to reality.Based on these theories and methods, several CDR circuits for above gigabit serial link are designed. The first is for 1.5Gbit/s SATA interface, using modified phase and frequency detector with delay cell. It is fabricated in 0.18μm CMOS process and tested, and the functions are realized. The second is for 1.25Gbit/s gigabit Ethernet, using modified quadrature clock half-rate phase detector, suitable for traditional charge-pump PLL. It is manufactured in 0.18μm CMOS process and tested, the functions are correct and power dissipation is only about 30mW and output peak-peak jitter is 69ps. The third is for 4-channel 10Git/s Ethernet, using parallel structure and transition-sensitive phase detector to reduce working speed. Jitter reduction is considered and the circuit is verified by simulation.Based on the above research, further research for high-speed broadband CDR, a dual-branch structure CDR is proposed, it is designed in 0.18μm CMOS process and now in fabrication.