Research And Design Of 25Gb/s Reference-Less Full-Rate CDRs In 40nm CMOS Technology

5G communication,super data center,broadband metropolitan area network and local area network support the booming development of mobile Internet,Internet of things and cloud computing,etc.,and 25 G or even 100 G,400G ultra-fast optical transceiver is one of its core basic modules.Ultra-high speed data transmission will lead to serious signal distortion at the receiving terminal,and the clock data recovery circuit(CDR)used in the transceiver to recover high-quality clock and data from the distorted signal is particularly important.In this thesis,the standard 40 nm CMOS technology is adopted to research and design two full-rate 25Gb/s CDR circuits without reference clock,and the 25Gb/s CDR can also be applied to ultra-high-speed optical transceivers such as 100 G and 400 G through multi-channel parallel.A multi-loop full-rate CDR circuit without reference is designed.By connecting the control branch of the frequency discriminator loop and the integral control branch of the phase discriminator loop into the coarse control terminal of VCO,and the proportional control branch of the phase discriminator loop into the fine control terminal of VCO,on the one hand,the wide acquisition range and high jitter performance can be realized simultaneously,on the other hand,the loop locking speed and the smaller filter area can be achieved.CDR circuit is mainly composed of full-rate Bang-Bang frequency and phase detector(PFD),quadrature clock output four-stage ring voltage controlled oscillator(VCO),three voltage/current conversion circuits(V/I)and loop filter(LPF).Among them,the two-terminal control ring VCO adopts a new type of inverter tuning mode,which can not only obtain a wider frequency tuning range,but also improve the tuning linearity.The layout area of the CDR is 206?m×140?m,and the power consumption of the core module in the circuit is about 88 mW.Finally,under different process angles and different temperatures,the simulation results show that the maximum jitter of the clock signal extracted by the circuit is 4.0 ps,the maximum jitter of the data signal is 3.5 ps,the minimum swing of the clock signal is 700 mV,and the minimum swing of the recovered data is 450 mV.A dual-loop CDR circuit with low jitter 25Gb/s full-rate and no reference clock is designed.The CDR circuit mainly includes a new low-jitter PFD,a quadrature-coupled LCVCO(QVCO),V/I,and LPF.Among them,the new low-jitter PFD combines the advantages of the full-rate Bang-Bang type PFD with the Alexander PD.On the one hand,the frequency discrimination function can be realized,on the other hand,the three-state phase-detection output can also be realized to solve the problem of loss of lock caused by long-connected “0” “1” data input and to improve loop jitter performance.A single LC parallel resonator in QVCO is connected to the negative-resistance generation circuit by means of a capacitive ac coupling of the variable capacitance,so that better tuning linearity can be obtained by changing the dc bias voltage while increasing the tuning range.The layout area of the CDR is 318?m×260?m,and the power consumption of the core module in the circuit is about 77 mW.Finally,under different process angles and different temperatures,the simulation results show that the maximum clock jitter is 5.0ps,the maximum clock jitter is 4.0ps,the minimum swing of the clock signal is 300 mV,and the minimum swing of the data at the recovery point is 400 mV after the simulation of different process angles and different temperatures.