A 1.25Gb/s Clock And Data Recovery Circuit Used In Gigabit Ethernet

Serial link technique is the main method used for backbone data communication. The clock recovery circuit (CDR) is the important building block of the receiver, whose performance decides the overall receiver performanceSeveral factors affect the signal characteristics at the receiver end. The media attenuates the high-speed data, and bring on inter-symbolic interference and results in input jitter for receiver. The function of CDR is to extract the clock from the jittering data, which needs to find out the optimum sampling point. Closed-loop CDR is based on the principle of phase-locked loop, and it has good characteristics in jitter tolerance and attenuation, which is suitable for high-speed serial link.Different serial link applications have different performance requirements for the CDR. Building block choosing and performance optimization is made accordingly. The dynamic characteristics of CDR include input jitter tolerance, jitter output and lock-in speed, which are strongly related to the loop characteristics. Non-linear frequency detector introduces difficulties for loop linear analysis. To solve this problem, one method is linear approaching using small signal model, the other method is behavior modeling, which is more close to reality.Based on these theories and methods, a CDR circuit for 1.25Gb/s gigabit Ethernet is designed. Referenceless CDR structure is adopted, using frequency locked loop to accelerate the lock in time and enlarge the lock range. TSMC 0.18μm CMOS process is used to simulate and verified the circuit. Simulation results shows that the functions are correct and power dissipation is only about 30 mW, and output RMS jitter is 6.9 ps.