The Design And Implementation Of A Clock And Data Rccovcry Circuit Based On Phase Locked Loop

The clock and data recovery circuit is the most important module of the receiver inthe serial data communication. To cope with the continuous improvement of the serialdata rate，a clock and data recovery circuit based on bang-bang type phase locked loopis presented in this dissertation. It has a variety of advantages such as automatic phasealignment, adaptation of the multiphase clock sampling structure. The working data ratecan reach the maximum speed of the D-latch determined by the process. A novelanalysis shows that the bang-bang loop output jitter grows as the square-root of theinput jitter as contrasted with the linear dependence of the linear PLL.First, a simulink model of the bang-bang phase locked loop is presented.Combining with the results of the modeling, some relationship between the loopperformance parameters and the design variables is achieved.Then, based on XFAB0.6um BiCMOS process, the blocks of the CDR circuit aredesigned. These designed circuits and modules such as phase detector, loop filter,VCO and frequency divider are simulated in Spectre. Simulation results show that thedesigned bang-bang phase detector shows a good phase comparator function of theserial data signal and the clock signal. The designed dual-path loop filter which includesa proportional path and an integral path achieves the desired functionality and goodperformance. a dual-loop VCO designed based on phase interpolation delay unitachieves a4to1output frequency range of600MHz to2.4GHz. The phase noise is90dBc/Hz@1MHz. The designed frequency coefficient variable frequency dividerachieves the desired function and speed performance.Finally, the designed clock and data recovery circuit is implemented by XFAB0.6um BiCMOS process. The test results of a serial data communication system whichintegrate the designed clock and data recovery circuit are presented. Test results provethat the designed clock and data recovery circuit realized the desired functionality. TheJpp of the recovered clock is32ps, and the jitter of the recovered data is0.04UI. All ofthe parameters achieve the design specification.