Research And Design Of High Power-efficiency Clock And Data Recovery Circuits

The bandwidth of communication interfaces is required to be increased in order to deal with the rapid growth of data volume in modern communication system.Traditional parallel topology has been replaced gradually by serial communication technology,which has been utilized as the mainstream technology for high-speed communication interfaces due to its advantages of high transmission rate,strong anti-interference ability,and less occupied channels and pins.The Serializer/Deserializer(Ser Des)interface is one of the common serial communication technologies,which is widely adapted for applications in display,storage,data exchange,etc.In the Ser Des receiver,the system communication capabilities are determined by the speed and jitter of the clock and data recovery(CDR)circuits.Meanwhile,as a high-speed,power-hunger module,it is vital to reduce the power consumption of CDR circuits in the premise of meeting application requirements.Therefore,it is significant to conduct research of high power-efficiency CDR circuits in the Ser Des field.The noise can be suppressed by the CDR architecture based on phase-locked loop(PLL),which has the advantages of low complexity and easy integration.It has been widely used in applications with a code rate of around 10Gb/s.This dissertation focuses on the research and design of PLL-based CDR with 12.5Gb/s non-return-to-zero(NRZ)input.The main works and innovations of this dissertation are as follows:(1)Based on the research of CDR working principle and jitter model,a high-efficiency half-speed architecture with binary phase detector is selected.Then,a high-efficiency jitter suppression technique based onΔΣmodulator are proposed by filtering out unnecessary frequencies components and reducing the accumulation of quantization noise to tackle the problem of jitter degradation caused by quantization noise in the binary loop.With the proposed jitter suppression technique,the system jitter performance is optimized.The simulation results show that the proposed technique reduces the jitter by 75%with additional power consumption of0.4m W.(2)The principle of theΔΣmodulator is analysed,especially the multi-stage noise shaping(MASH)architecture.Based on that,a high-efficiency MASHΔΣmodulator which has low spurs with the adaptive length extension technique is proposed.Based on a feedforward structure,the accumulators in the proposed MASH are fully utilized to get an adaptive feedforward gain to compensate for the sequence length loss due to input.The proposed MASH can extend the output sequence length to the maximum under any input,thus to reduce spurs.The results of modelling and simulation based on MATLAB show that the quantization noise of the proposed MASH is distributed widely with no noticeable spurs.(3)With the research of low-power supply-insensitive technique,a multiphase clock generator(MCG)based on the current-reused voltage-controlled oscillator(VCO)and divide-by-two frequency divider(FD)is designed.By utilizing the proposed mutual power-supply rejection(M-PSR)technique,a voltage regulator is embedded into the structure to further decrease the supply-sensitive without the requirement of extra voltage headroom.The circuit is fabricated in a 28nm CMOS process.Measurement results indicate that the MCG achieves an output frequency range from 5.9GHz to 6.3GHz with the power consumption of 1.8m W.The supply sensitivity is0.129m UI/m V.This work has a figure-of-merit with supply sensitivity(FOMss)of-243.3d B.Based on the above research,a CDR circuit has been taped out based on a 28nm CMOS technology.The complete chip area including I/O PAD is 0.858mm~2(0.78mm×1.10mm).The area of CDR core is0.21mm~2.The chip is measured with wire bonding on the PCB.The measurement results show that the recovered 6.25GHz clock has the peak-to-peak and rms jitter of 9.41ps and 1.014ps respectively,and it can cover the input frequency range from 11.8Gb/s to 12.6Gb/s.The recovered 195MHz data after DEMUX has the peak-to-peak jitter of 0.137UI.The power consumption of the CDR core is only 4.5m W with the bit efficiency of 0.360p J/bit.