The Design Of High-speed And High-precision Pipeline ADC

The analog-to-digital converter(ADC)can convert continuous analog signals into discrete digital signals and plays an important role in communication systems.Nowadays,the requirements of communication systems for signal processing are constantly developing in the direction of high speed and high precision.Among the ADCs with many structures,pipeline ADCs are widely used in the field of wireless communication because of their high speed and accuracy characteristics at the same time.In this paper,a 14-bit 100MSPS pipeline ADC with no sample-and-hold structure is implemented based on the eastern 0.18?m BCD process.The article first analyzes the structure principle of the pipelined ADC and the redundant bit digital correction algorithm,discusses various non-ideal effects in the pipelined ADC.The article establishes the pipelined ADC power consumption model based on the thermal noise constraint and the operational amplifier bandwidth constraint in the non-ideal effect.According to the model results,The final overall pipeline ADC adopts 2.5bit*3+1.5bit*5+3bit level allocation,a total of 9 levels.Aiming at the influence of DAC capacitance mismatch,a front-end correction technique is proposed,which has been verified to effectively improve the dynamic performance of ADC.To reduce power consumption,the design adopts a sample-and-hold structure.Based on the analysis of the influence of the sampling time deviation and sampling network bandwidth mismatch under this structure,a first-stage pipeline sub-ADC and MDAC sampling network structure is proposed.In terms of circuit design,this paper analyzes the impact of memory charge in MDAC and proposes a memory charge elimination structure,which stabilizes the working state of the previous-stage pipeline operational amplifier;the operational amplifier in the first-stage pipeline adopts a two-stage fully differential structure,and auxiliary op amp is added to increase the gain.It has been verified that the op amp can achieve an open-loop gain of105d B or more and a closed-loop-3d B bandwidth of 400MHz or more under each process angle,which fully suppresses the non-ideal effects of the op amp.To ensure that the sampling network bandwidth is It remains unchanged under different input signals.The first-stage pipeline in this paper uses bootstrapped switch to reduce the change in on-resistance.Compared with the traditional structure,the bootstrapped switch designed in this paper adds fast turn-on and turn-off and Substrate bias effect elimination module,when the input signal frequency is within the Nyquist frequency range,the ENOB of the bootstrapped switch can reach more than 15.9bit;because there is no sample-and-hold structure,the comparator in the first stage of the ADC is out of adjustment The voltage must be small enough to reserve more error range for the sampling time deviation and sampling bandwidth mismatch.The first-stage pipeline in this article uses a comparator with a pre-amplifier and input offset cancellation structure.The response time is 285ps and the offset voltage standard deviation about 1.83m V.Compared with the first stage,the comparator in the later stage pipeline has many fewer restrictions.Therefore,a four-input comparator with a pre-amplifier structure is used to reduce area and power consumption.The response time of the latter stage comparator is 90ps.The standard deviation of the offset voltage is about 5.67m V;the clock circuit in this article generates a three-phase clock signal,of which the two-phase non-overlapping clock signal is used to control the working state of the pipeline and complete the bottom plate sampling,and the third-phase clock is used to generate and eliminate the memory charge signal of.The overall ADC working voltage and full-scale voltage are 1.8V,the power consumption is138.6m W.The width of the layout is 0.6mm,the length is 1.4mm,and the area is 0.84mm~2.The simulation results show that the pipeline ADC designed in this paper has a SFDR of87.30d B,an SNDR of 79.07d B,and an ENOB of 12.84 bits at a low frequency input of9.716MHz;when the input signal frequency reaches 49.75MHz,the SFDR is 85.91d B and the SNDR is 78.69d B,the ENOB is 12.78 bits.