Sample-and-Hold And MDAC Circuits For Pipeline ADC

Pipeline Analog-to-Digital Converter(ADC) have a good compromise on the speed, accuracy, power and area, capable of taking into account the speed and accuracy, thus pipeline ADC as the main structure to achieving high speed and precision ADC, it was applied in a wide range of field such as digital communications, data field access and video processing. S/H circuit(Sample-and-Hold circuit) and MDAC(Multiplying Digital to Analog Converter) circuit are the core part of the pipeline ADC, their performance determine the overall performance of pipelined ADC, Therefore, the study of S/H circuit and MDAC circuit have a very important significance for the realization of high-speed and high-precision pipelined ADC. The S/H circuit and MDAC circuit adopted in a 12 bit 50M sample/s pipeline ADC is designed in the paper.The basic principles of the S/H circuit and MDAC circuit, including the structure and non-ideal error of S/H circuit and MDAC circuit are firstly analyzed in this paper. And then the indicator, researched the structure and designed circuits are determined according to the requirements of Operational Amplifier(Opamp). Finally the circuits design, include main amplifier, N-type auxiliary amplifier, P-type auxiliary amplifier, bias circuit and common-mode feedback circuit, and the simulation of the overall Opamp are completed. Then the S/H circuit, bootstrap switches, bottom plate sampling technique, non-overlap clock circuit, comparator and sub-ADC circuit were researched. The associated circuit simulation results were presented. Then the research work was focused on the design of the 2.5 bit MDAC circuits and analysis of the structure and working principle of the first-stage MDAC circuit. The transfer function of the MDAC circuit was derived. Finally, the layout of the MDAC circuit was completed.This paper designed a S/H circuit and MDAC circuit for 12 bit 50MSPS pipeline ADC in Cadence Spectre software using SKYSILICON Co. Ltd CD035 MVA 0.5?m CMOS process. Simulation results shows that Opamp's open-loop DC gain is 90.86 dB, the GBW is 663.6MHz, the PM is 58.65°, slew rate are 2437.6V/?s at rising and 705.5V/?s at falling, S/H circuit and MDAC circuit are proper functioning at 50 MHz sample frequency. All of the parameters match the 12 bit 50MSPS pipeline ADC's requirements.