The Design And Research For Key Cells Of 10 Bit 100MSPS Pipeline ADC

The real world of human’s life are physical quantities which is called analog signal,whilewith the development of modern technology, the digital processing technology become more andmore matured. As digital processing has many advantages, generally people want to use digitaltechnology to deal with the real physical quantities. And it is required that the analog signal of thereal word to be converted to digital signal for processing. The ADC (Analog-to-digital converter)is the key component that connect the real world and digital computing areas. Compared to othertypes of ADC, pipeline ADC can not only guarantee high-speed work, but also achieve more than8-bit resolution.So it has became the mainstream of the high-speed, high precision analog todigital converter. This paper firstly describes the working principle and the classification of theADC and then research the 10bit 100MSPS pipeline ADC design technology, analys the sourcesof pipeline ADC’s error and non-ideal factors, and design the key cells of 10bit 100MSPSpipeline ADC in CSMC 0.18μm 1P6M CMOS mixed-signal technology, the work that hascompleted are summarized as follows:(1) The capacitor flip-around architecture sample and hold (S/H) circuit is completed toachieve high speed front end sampling, the bottom plate sampling techniques are adopted toreduce clock feed-through reduction and charge injection effects. Bootstrapped Sampling Switchis designed to Improve the linearity of the sample and hold circuit. The high-speed high-gain fullydifferential operational transconductance amplifier with gain-booster which could be used insample and hold circuit and the first class multiplying digital-analog Converter (MDAC) circuit isdesigned.(2) The first stage converter circuit of 10bits 100MSPS pipeline ADC is completed include1.5bit/stage subADC circuit and multiplying digital-analog converter (MDAC) circuit. Thedynamic comparator is adopted to reduce reduce the power consumption of each stage.Bootstrapped Sampling Switch and bottom plate sampling techniques are adopted to reduce clockfeed-through reduction and charge injection effects.(3) The clock generator, voltage reference ,bias current source and other auxiliary modules of10bit 100MSPS pipeline ADC are completed. The delay locked loop is used to generate twophases non-overlapping clock and the auxiliary clock. High precision low temperature driftbandgap voltage reference adopted high-temperature compensation technology which is used toprovide reference voltage and bias current for the ADC system is completed.In this paper, all the circuit modules’ layout and post simulation are done. The post simulation results show that the S/H circuit achieves SNDR of 78.8dB, ENOB of 12.8, SFDR of79.6dB; the subADC circuit achieve the function of analog to digital;The MDAC circuit achievethe function of sample and hold, subtraction, and 2 times gain. All the designed circuit modulesmeet the 10bits 100MSPS Pipelined ADC system’s requirements.