Low-voltage High-performance Sample / Hold Circuit

With the continued developing of digital process scaling down and the demand of system-on-chip, low-voltage technology has became one of the trends of achieving high-end Analog-to-Digital Converters (ADC). At the same time, progress of high-definition television and wireless radiofrequency technologies has also requested higher ADC's speed and accuracy. So, study of low-voltage high-performance Sample-and-Hold(S/H) module which has an important impact of ADC's speed, resolution and power dissipation is a hot subject.In this thesis, stemming from S/H basic theory, the difficulties and related technical methods of achieving high-performance S/H circuit under low-voltage are researched and discussed from three areas which are sampling switch, Operational Transconductance Amplifier (OTA) and S/H circuit topology, and, designs and authentications are also gived based on SMIC Si 0.18μm CMOS process.Firstly, the constrained interactions between several main parameters of S/H circuits and the declining supply voltage V_DD are derived. If resolution N is kept constant, the minimum limited noise voltageσmust be lower, and speed determined by either bandwidth GBW ox sampling frequency f_s will drop by different levels. Power dissipation will rise inversely if all of process linewidth L, N, GBW and f_s are kept constant, so speed and resolution need to be sacrificed to save the power. In deep sub-micro process power dissipation will be reduced if all of N, GBW and f_s are kept constant when L is small enough that V_DD scales down linearly with it.Secondly, on the basis of aggregating and comparing main non-ideal factors and relative technical solution, a high-linearity No-Feedthrough Double-Side Symmetrical (NFDSS) gate-voltage bootstrapped sampling switch is presented. By testing eight different kinds of switches in simulation under 1.8V-supply voltage and comparing the curve of the on-state resistant R_on with full-swing input, it is got that this NFDSS switch with R_on less than 4Ωwhich is the smallest and the most stable of all is more suitable for low-voltage high-performance applications.Thirdly, by the confirmation of the gain-bandwidth design rules of gain-boost and no-capacitor feedforward compensation technology of OTA suitable for high-performance S/H system, a high-gain wide-band large-swing Cascode Gm-FeedForwrd (CGFF) two-stage differential OTA is proposed, of which the performance is better than that of traditional telescope or folded cascode OTA and Miller compensation two-stage OTA.Then, from Correlated Double Sampling (CDS) theory and comparative analysis of different CDS technologies, the correlation in the principle with S/H is revealed, and, a CDS-S/H topology is got from a traditional charge-transferring S/H topology combined with a noninverting wide-band CDS topology, which can cancel the dc error such as OTA's offset, low frequency noise and charge injection of switches and achieve much lower gain-error synchronously.Finally, three design strategies are also proposed for 12bit-resolution 100Msps-speed S/H circuit by different configurations with the above modules under 3.3V-supply voltage. The optimized simulation results show that strategy I of the NFDSS gate-voltage bootstrapped sampling switch and 95.47dB-gain 760MHz-bandwidth 59.56°-phase margin gainboost cascode OTA attains 84.24dB-SFDR, strategy II has 10.69mW lower power dissipation and 6.3% longer hold time than strategy I with the replacement of the 90.39dB-gain 726.9MHz-bandwidth CGFF-OTA, and, by using the CDS-S/H topology, strategy HI gets the smallest gain-error 0.1199%o, of which the OTA is the simplest and only needs 69.96dB-gain.So, all of the three strategies have achieved 12bit 100Msps S/H circuit and verified the feasibility of the technical methods introduced in mis paper, which overcome the performance bottleneck of the constrained interactions between specifications such as N, GBW,f_s, power dissipation et al. from different angles and offer some optional ways towards solving design problems caused by low-voltage.The above theory and methodology are suitable for the front-end S/H module of high-performance pipeline ADC and further research and discussion of relative technical aspects.