Research And Design On Sample/Hold Circuit For 12-bit 40 MHz Pipeline ADC

In recent years, Pipeline ADC is widely used in the portable video device and wireless mobile, due to its high speed high resolution and low power consumption. Sample/Hold Circuit (S/H) is the most forward part of Pipeline ADC, and its speed resolution and power consumption will mostly determine the performance of the whole ADC. So to study and design a Sample/Hold Circuit with high speed high resolution is very crucial to the Pipeline ADC.Firstly, we introduce the Sample/Hold Circuit, analyzing its working principle performance index and the source of error. And then, we analyze the important part of the S/H in detail.Based on the studies, the S/H we designed uses the fully differential flip-around structure, the fully differential topology can lower the common mode noise from the bulk, and also can lower the distortion caused by many non-linearity factor, but it makes the layout more complex and needs common mode feedback circuit. The flip-around structure has lower noise and power consumption, and hasn't the gain error caused by the matching problem of the capacitances. Bootstrapped switch with dummy device is used to minimize the nonlinearity caused by the MOS switch. A folded cascade operational transconductance amplifier with gain-booster circuit is used to enhance the speed and precision performance.The Sample/Hold Circuit is finally simulated and analyzed under the Cadence environment based on XFAB's 0.35μm CMOS process. The result shows that the Sample/Hold Circuit can achieve 13-Bit resolution under 3-V supply voltage and 40 MHz sampling rate, which can be used in the 12-Bit 40 MHz Pipeline ADC.