Sample-and-Hold And MDAC Circuits For Pipeline ADC

Pipeline Analog-to-Digital (ADC) is widely used in high-speed and high-resolution applications because of its superior trade off among speed, area and power. Sample-and-hold (S/H) and multiplying digital-to-analog converter (MDAC) circuits are key functional blocks in pipeline ADC. The thesis studied the S/H and MDAC circuits of pipeline ADC. Based on ASMC 0.35μm 3.3v/5.0v BiCMOS process, using the"SHA-less"structure, a 3-bit 1st MDAC including the S/H circuit is designed. The MDAC can be applied in a 14-bit 80MHz pipeline ADC.Based on discussing the structure of S/H and MDAC circuits, the circuits involved in the S/H and MDAC are designed. The circuits design covers: BiCMOS fully differential oprational amplifier (OPA) with switched-capacitor common mode feedback (CMFB), BiCMOS input buffer, bootstrapped switch, etc. Simulation has been done to clarify the circuit performance. Simulation result shows that the DC gain of the OPA is 118dB, the gain bandwidth is 1.65GHz and the phase margin is 59°. When the input signal is 8.515625MHz and the sampling clock is 80MHz, the SNDR and SFDR of the output signal is respectively about 73.3dB and 78.2dB, which achieves 12-bit accuracy and meets the requirement of the system.