Research And Design Of Fast-locking ADPLL Based On Piecewise Tuning Code Estimation

With the booming development of the Internet of Things,the continued demand for low cost and low power of wireless communications drive research of the RF front-end,among which the phase-locked loops(PLLs)play an important role.All-digital phased-locked loops(ADPLLs)are preferred over their analog counterparts in nanoscale CMOS technology due to their flexibility,configurability,small area and easy portability.Meanwhile various protocols in the field of wireless communication have strict requirements on settling time,which makes fast locking ADPLLs an important subject in the field of PLLs.An all-digital phase-locked loop that can achieve fast locking is researched and designed in this dissertation.The main work is as follow: 1.An improved algorithm of tuning code estimation,combined with binary search,is proposed to achieve fast locking.The improved code estimation adopts piecewise linear method to fit the relationship between tuning codes and output frequencies.The influence of non-ideal factors on the fitting effect was analyzed through mathematical derivation and MATLAB modeling,and the fitting parameters were optimized.The proposed algorithm speeds up the locking in the coarse tuning stage,and the locking time is reduced by nearly 82% compared with that of the traditional tuning code estimation;2.A method of estimation of the key fitting parameter,digitally controlled oscillator(DCO)gain is proposed,which enables the system to extract the DCO gain at different process autonomously.A scheme of low complexity to calculate the codes is proposed on this basis,which makes the division operation can be realized only through the shift operation;3.A method of error correction for frequency and phase detection is proposed to eliminate the error of the value of one reference frequency,which is caused by the phenomenon of metastability in synchronously sampling.This method not only reduces the complexity of the circuit but also improves the accuracy of the result of frequency detection,so that the system can adopt higher loop bandwidth and shorten the settling time.The proposed ADPLL is designed in TSMC 65 nm CMOS process with an area of 830μm×270μm.The simulation results show that the circuit is locked within 3μs when the frequency of the reference clock is 32 MHz.The tuning range is 4.43-5.46 GHz while the rms jitter is 1.3ps.The total power dissipation is 4.7mW.