A Noval Fast-locking Adpll Based On Newton's Method

Phase-locked loop is widely used in the national life and military fields,such as mobile phone,computers,radar,communicate equipment,aerospace and so on.In addition,PLL can also provide high-speed synchronous clock for the system,or extract timing information in the data stream.Today,with the development of SOC,the traditional structure of PLL has been unable to satisfy the requirements of the high-performance system.High-performance,low power and fast-locking have become a new trend in the design of PLL.The ADPLL has become the hot topic in the research because of the stability,portability and flexibility.The main advantages and innovations of the ADPLL are as follows: 1.A fast locking algorithm which is based on dichotomy is proposed and used in the coarse-tuning locking mode of ADPLL.The locking time of new algorithm have no concern with target frequency and Filter's bandwidth,it is only related to output frequency range and frequency resolution.The new locking algorithm can reduce the locking time by about 90% when the Frequency Control Word(FCW)of Digital Control Oscillator(DCO)is more enough;2.A dynamic median locking algorithm based on dichotomy is proposed and used in the fine-tuning locking mode of ADPLL.The algorithm can dynamically adjust the locking speed according to the target frequency and the time the locking process has taken,in order to shorten the locking time;3.According to the new algorithm,a new structure ADPLL is designed.The ADPLL removes the PFD,DLF and uses a fully customized control circuit to adjust FCW of DCO to achieve fast locking effect.When the number of FCW is not more than 2,the ADPLL only needs n reference clock cycles to complete the coarsetuning of FCW.The proposed ADPLL was designed in SMIC 180 nm CMOS process.The post simulation results showed a lock range of 640-to-1920 MHz with a 40 MHz reference frequency.The ADPLL core occupies 0.03817 mm and the greatest powerconsumption,29.48 mW,with a 1.8 V supply and the most locking time is 23 reference cycles,575 ns,at 1.92 GHz.And when the ADPLL output 1.28GHz-1.6GHz clock,the locking time is the shortest,and is 9 reference cycles,225 ns.The simulation results,with respect to the recently proposed high-performance ADPLLs,show advantages of small area,short locking time,very high and wide output frequency.