ADPLL Design And Application Based On FPGA

With the development of modern integrated circuit technology, phase locked loop has become a significant component of integrated circuit, which makes the research of phase-locked loop is very valuable. However, most of the traditional phase locked loops are analog-digital mixed circuits, there exists some compatible problems with systems-on-chip digital circuit on the process level. Therefore, the DPLL design which is compatible with digital circuits is crucial. The ADPLL design can take the procedures of digital circuit design, i.e, description language is written first, followed by logic synthesis, which makes ADPLL highly portable.Firstly, this paper describes the basic principles of phase-locked loop and then summarizes the advantages of the DPLL. Many advantages of digital phase-locked loop are apparent .The capture time of ADPLL is very short, which make the research of ADPLL attractive, due to its digital characteristics.At the first, we determine the main components of DPLL circuit on the basis of the analysis of phase-locked loop circuit and give each unit of the circuit design, and the key parameters of the program are also choosen carefully. Next, This paper gives a detailed description of the working process, combined with the simulation waveform of digital phase locked loop. Finally, we test the phase-locked loop circuit on the FPGA platform, and results make it clear that the ADPLL's performance gain is great, in line with our expectations.In addition, this design can detect the phase errors. Later, We give a brief analysis of function stability, tracking performance and noise characteristics of the circuit, and the corresponding solutions are given. Finally, the paper introduces the application of the ADPLL: FSK decoder. We verify its properties through simulation on PC, and discuss several related issues in practical applications.