| DPLL posesss the advantages of high reliability, low area and cheap price, and resolves problems of analog circuit such as DC offsets, is susceptible to supply voltage and temperature changes in the environment affect, etc.In the other ways, DPLL has a natural ability for real-time processing of discrete values. Thus, DPLL has become the development direction of the PLL technology, research in the area of digital equivalent implementations of analog and RF circuits is in great demand now. As a result, this paper will study and analysis PLL constructed by all digital blocks.In this thesis, I design two kinds of ADPLL that have different structure of DDS. We both use analytic filter to acquire in-phase component and quadrature component from sine-wave input signal, and muti-stage pipeline CORDIC structure based arctangent structure to acquire phase information from in-phase component and quadrature component of the origianl input signal.We apply a phase unwrap structure to acheive large range of phase error detection and low lock-in time. We utilize the traditional second-order proportional-integral filter as our loop filter. By using the dominant pole method, we could transform the DPLL with high order loop delay to a second-order system to approximate our DPLL to second-ord system on transient behavior and make our loop filter suitable for DPLL with high-order loop delay. We exploit DDS as our DCO, and design LUT based DDS and CORDIC based DDS one after another.Modules and overall of above design are behavioral modeled and RTL designed in this paper. Then in the ASIC design, I adopt suitable structure which is with second-order analytic filter, 16-stages pipeline CORDIC structure based phase-acquire-structure and DDS. I implement ASIC design based on process of SMIC 0.13 mm and ASIC design tools of synopsys. Our post-simulation result is almost the same as our pre-simulation result. The lock-in time is about 4 ms, phase error is about 6.4312°, and chip area is 1*1 mm~2. |
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