Design And Analysis Of Fast-lock Phase-locked-loop

As an important part of modern clock circuit, Phase-locked loop has become anecessary module of the large-scale integrated circuit. The circuit, which has beengenerated by the phase-lock clock, is almost adopted in all the digital integratedcircuits, providing internal high-speed clock. The clock signal is the key in digitalcircuits. An important indicator measuring the quality of clock distribution lies wherethe delay transmission between the module and phase shift occur. As process-sizeshrinks, integrated circuits are developing towards the direction of the on-chip systemand the chip area is also increasing. However, among the internal chip, the delay dueto the interconnection of various modules tend to lead an accumulation of signaldelay, which is to cause serious timing error. What is worse more, a dysfunction ofcircuit will bring out. Lock-phase accuracy and locking time are two inconsistentdesigning indexes in traditional phase-locked loop. Therefore, we have tocompromise in order to consider the requirements of the two parameters. To betterthis problem, this paper is written to design a high-speed phase-locked loop, speedingup the lock time while accuracy remains unchanged.To start with, this paper reveals the structure and basic principle of phase-lockedloop circuit. In terms of the common charge pump phase-locked loop and digitalphase-locked loop, the various modules of their function, the mathematical model andtransfer function are analyzed respectively in detail. Also, non-ideal factors arepointed out in this paper.Secondly, after a thorough understanding of the principle of phase-locked loop,a high–speed phase-locked loop is designed. Modular-designing approach has beenadopted while designed. The general loop is firstly designed in view of the modular.Frequency divider, phase discriminator, reversible counter, the voltage-controlledoscillator are processed with circuit design in succession. Further more, structures andprinciples of the basic circuit of each module are revealed in this paper.0.6um,standard CMOS process model is adopted, and Cadence Spectre is applied to carryout simulating-tests upon each module. Finally, according to the device parameters that meet the requirements of thedesign, layout drawing, electrical inspection and circuit matching are to be carriedout.The innovation point of this paper mainly incarnate in the following three points:1．An innovative point of this article is that it has been optimized in this designthat trade-offs and design focus on the precision of phase lock or lock timing of thetraditional phase-locked loop are needed. Corresponding adjustment of step length isdifferent according to the different range of the phase error in frequency so that theaccuracy of the phase lock loop and speed are ensured. Apart from the oscillator, anyother circuits are supposed to be made via utilizing digital circuit, which canguarantee the stability of the circuit.2．The expand applications of PFD. Traditional PLL usually only discern the phaseerror between outside clock and chip clock. The phase discriminator of this chipdiscriminate different frequency in order to judge the phase/frequency error. This kindof phase discriminator can be used in different error ranges, also can adjust the phasefrequency and accelerate the lock time.3．Design a kind of reversible counter to match with the different output range ofphase discriminator. The count step changes follow the different of error range. Thereversible counter is a binary weight variable reversible counter which is combinatedwith common UP/DN counter. The design purpose of this is to change the outputbinary digital signal into the control of VCO, then change the frequency of VCO.