Design And Realization Of The High Speed ADPLL Based On The 55nm Process

ADPLL as an important part of modern clock circuit,has become the indispens-able one module in very large scale integrated circuit.Almost all digital integrated circuits using clock generating circuit using ADPLL to provide on-chip high speed clock.At first,this paper simply introduces the development history of ADPLL technol-ogy and it's application value and theoretical significance.The concept,composition,principle purpose and classification of ADPLL are introduced in details.This paper mainly introduces the PFD(Phase-Frequency-Detector),TDC(Time to Digital Convert-er and DCO(Digital-Controlled Oscillator).In the paper,I has carried on the design and improvement,and performance analysis for the four modules circuits respectively.And compared with the performance of the existing circuit structure,which testified in this paper,the designed circuit and its optimization modification is effective.All the design is based on 55 nm CMOS technology.I has finished the circuits design,simulation and layout design using down-top design method.The key point is the design of the digital controlled oscillator and time code conversion.Due to the effects of parasitic parameters and PVT,the DCO gain will change,which will infect the circuit stability.In addition,in the last chapter,I first briefly introduces wiring rules of the landsca-pe design layout,then the landscape design of this project are briefly introduced.At last,I do the whole simulation of phase-locked loop.