Design Of All-digital Phase-Locked Loop Based On Time-to-Digital Converter

With the development of computer,signal processing and communication technology,digital integrated circuits have increasing demands on system clock.Phase-locked loop is the key circuit technology to provide clock for digital system.With the development of semiconductor manufacturing technology,analog circuit structure of phase-locked loop has been unable to meet the requirements of modern digital integrated circuits,but all-digital phase-locked loop(ADPLL)which has the advantages of high integration,high portability,strong anti-interference ability,short design cycle and being programmable become a hotspot in the field of PLL.The design of ADPLL based on time-to-digital converter(TDC)is studied in this paper.The ADPLL uses a structure based on TDC.This structure is consist of TDC,digital controlled oscillator(DCO)and phase frequency controller,in which the TDC uses a vernier delay chain to improve its resolution.The whole circuit uses both full-custom and semi-custom design methods.Firstly,a behavioral model of ADPLL is constructed and the function of ADPLL is verified though the analysis of the structure and principle of ADPLL.Then,based on the verification of function,the system and circuits of ADPLL are designed and simulated by using mix-signal simulation to verify the pre-layout performance.Finally,the ADPLL layout is completed and post-simulated.The ADPLL can provide a clock,of which the highest frequency is 1.5GHz,based on 0.18?m CMOS technology.The chip area is 0.8mm2,the post-layout simulation results show that its output frequency ranges from 605MHz to 2.03GHz.The peak-to-peak value of its period jitter is less than 22ps and the RMS of its cycle-to-cycle jitter is less than 5ps at 1.5GHz.The power dissipation is less than 20mW with a 1.8V power supply at 1.5GHz.The simulation results meet the target requirements.Under the trend of developing large scale integrated circuits,the proposed ADPLL structure is of great and significant value to implementation of signal processing and communication system.