Design Of Fast Locked PLL Based On System Of Back Lighting

The diversity of PLL applications makes it ubiquitous in various chip systems,for example,as a clock generator to generate the square wave signal needed for digital circuit operation,or for frequency modulation and demodulation in communication systems.The PLL designed in this paper was utilized in system of back lighting,which requires fast-locked in and low jitter.To realize low jitter,a narrow bandwidth is needed,but in another word,it would cost a lot time to locked in.Aiming at this problem,a solution was proposed in this paper to overcome this dilemma.The top-down design process was used in this paper.We use the established behavior model of PLL to design the extension circuit which can reduce the locking time,and we design the locking detection circuit to verify the effect.Based on the Magna chip 0.18 um process,we design the schematic of each module by the software named cadence.And after lots of simulations,we verify the reliability of PLL,and realize the power supply voltage of 1.6V and the input clock frequency range.For PLL with 4MHz ～ 12 MHz input frequency range,feedback frequency division ratio range of 2 ～ 15 MHz and output frequency range of 24 MHz ～ 60 MHz,under different working conditions,the acceleration effect of locking time is about 40%,and the period jitter of output under typical working conditions is 0.16% of the output clock period.In addition,a reference current module is designed for the whole loop,which provides a reference current insensitive to temperature.The output current does not change more than 1.5% of the current at room temperature.Finally,the layout matching technology is discussed,and the layout of the analog circuit module in the loop is drawn.