| With the development of science and technology, the semiconductor integrated cir-cuit has entered the age of very deep sub-micron and nano-micron CMOS. The integratedcircuit system has an increasingly high level of integration and more complex functions.All these new situations present enormous challenges to the traditional analog and RFcircuit design. Consequently, digitalization of the analog circuit and the digital-aidedtechnique are widely used and becoming a trend. Digital RF is an important approach torealize the digitalization of the analog circuit. The all-digital phase-locked loop (ADPLL)frequency synthesizer and ADPLL-based single chip digital transceiver, proposed by TIcorporation, are the typical designs in the digital RF area. In this dissertation, the ADPLLfor digital RF application is conducted and the principal contributions of this dissertationinclude:In this dissertation, an analysis method of the lock process of the ADPLL is proposedbased on the time-domain model. A quantitative lock time analysis of the ADPLL ispresented. The calculation methods of the lock time of the type-I, type-II, and multi-modeADPLL are proposed. An analytic expression for the lock time of the type-I ADPLL isderived under special conditions, which shows a quantitative relationship between thelock time and the loop parameters and the input signals. Simulation results show that ourproposed methods realized using Matlab for the lock time calculation are10000x fasterthan VHDL simulation, and the average relative error is less than30%.In this dissertation, a novel counter-based mode switching controller (CB-MSC)is presented for the multi-mode ADPLL. According to the frequency dithering in theADPLL, the CB-MSC not only reduces the mode switching time, but also estimates andpresets the digitally controlled oscillator (DCO) tuning word for the next operation modeto accelerate its lock process. Simulation results show that the proposed CB-MSC canreduce the ADPLL's lock time by about37%.In this dissertation, a DCO tuning word estimating and presetting technique is pro-posed to reduce the lock time of the ADPLL. Two methods are utilized: one is to directlycalculate the tuning word using the ADPLL's reference clock frequency and the inputfrequency command word. A calibration mechanism is used to eliminate the efect of the non-ideal factors of the circuit. The other is to use the CB-MSC. By monitoringand analyzing the tuning word of the former operation mode, the CB-MSC generatesthe required tuning word for the latter operation mode. Simulation results show that theproposed technique can reduce the ADPLL's lock time by about50%.In this dissertation, a low power diferential delay line time-to-digital converter(DDL-TDC) is presented. The detailed components of DDL-TDC's power consump-tion are analyzed. Utilizing a clock gating circuit, the total power consumption of theDDL-TDC can be reduced by more than80%.In this dissertation, a fast locking ADPLL frequency synthesizer is designed and im-plemented in HJTC0.18μm CMOS technology for the digital RF applications. The DCOtuning word estimating and presetting technique and design-for-test method are utilizedin the designed ADPLL. Measurement results demonstrate that the proposed DCO tuningword estimating and presetting technique can efectively reduce the ADPLL's lock timeby about30%.The above contributions of this dissertation establish a firm basis for the researchand design of low noise, low power, and fast locking ADPLL frequency synthesizer andthe ADPLL-based all digital RF transceiver. |
