Research And Design Of Key Technologies Of Highprecision Successive Approximation Analog-to-digital Converter

With the rapid development of electronic integrated circuits in recent years,the data acquisition system is moving towards a faster and more accurate direction.The successive approximation analog-to-digital converter(SAR ADC)has the advantages of simple structure and easy integration,which makes it one of the research hotspots of ADC in recent years.In this thesis,a 16-bit 1MSPS(Samples per Second)SAR ADC is designed,the main contributions of the thesis are as follows:Firstly,based on the concept of charge conservation of capacitors,this thesis summarizes a charge conservation analysis method suitable for high-precision segmented capacitor arrays.Compared with the traditional series-parallel analysis method,the three-segment capacitor array can be quickly designed;the capacitor array is divided by integer bridge capacitors.It is a three-stage capacitive array,which reduces the area of the capacitor array in addition to satisfying the quadraticity between the capacitive arrays and is more conducive to the matching between the bridge capacitor and the unit capacitor;then,the redundant capacitors and the last repeated unit capacitors are added to the capacitive array to enhance the error correction capability of the SAR ADC and reduce the impact of noiseSecondly,this thesis analyzes the influence of MSB(Most Significant Bit)capacitor array capacitance mismatch on SAR ADC,and proposes a sorting and reconstruction scheme based on statistics to reduce the impact of MSB capacitor array capacitance mismatch.The SAR ADC is modeled by MATLAB and the proposed ordering and reconstruction scheme is verified.1000 times of Monte Carlo simulation results show that the average Spurious Free Dynamic Range(SFDR)of the sorting reconstruction scheme is 83.8d B and the signal-to-noise-distortion ratio is 83.8d B.The average value of Signal to Noise and Distortion Ratio(SNDR)is 77.8d B,the average value of SFDR is 104.2d B and the average value of SNDR is 74.0d B after the sorting and reconstruction scheme.Therefore,the use of sorting and reconstruction scheme improves SFDR by 20.4d B and SNDR Increased by 16.4d B,DNL(Differential Non-linearity)increased by 0.94LSB(Least Significant Bit)and INL(Integral Non-linearity)increased by 21.07LSB.The simulation results of MATLAB show the feasibility of the sorting and reconstruction calibration scheme.Thirdly,this thesis analyzes the influence of the parasitic capacitance near the bridge capacitor and the parasitic capacitance of the low-level capacitor array on the linearity of the SAR ADC,and proposes a floating node calibration scheme to reduce the parasitic capacitance by adding a calibration capacitor to make the actual equivalent weight of the low-capacitance array approach its ideal weight.Using MATLAB to verify the floating node calibration scheme,under the condition of unit capacitance mismatch standard deviation?=0.2%,1000 times of Monte Carlo simulation results show that the mean SFDR of the floating node calibration scheme is 87.9d B before calibration,the mean SNDR is 71.21d B and the mean SFDR of the floating node calibration scheme after calibration is 112.8d B,the mean SNDR is 96.2d B,so the floating node calibration scheme improves the mean SFDR by 24.9d B,the mean SNDR by 25.0d B,the DNL by 0.11LSB and the INL by 7.74LSB.To sum up,the results of 1000 Monte Carlo simulations show that the mean SFDR is 83.6d B and the mean SNDR is 73.9d B before using ordering and reconstruction scheme and floating node calibration scheme,and the mean SFDR is104.5d B and 89.3d B after the two calibration schemes are not used.Therefore,the two calibration schemes are used to increase the mean SFDR by 20.9d B,the mean SNDR by19.0d B,the DNL by 1.21LSB and the INL by 24.79LSB.The simulation results of Matlab show the feasibility of the two calibration schemes.Then,considering factors such as SAR ADC noise,accuracy,speed,etc.,this thesis uses a four-stage preamplifier circuit and a dynamic latch circuit to design a high-precision low-noise comparator with an offset voltage standard deviation of 1.87mV and equivalent input noise.voltage is 28mV.Then,the designed SAR ADC is simulated before PVT(Process,Voltage,Temperature)under the process of 180nm.According to the simulation results before PVT,the SNDR of the SAR ADC is above 95d B and the SFDR is above 103d B.The average current in 1000 conversion cycles is 8.1m A,plus the power consumption of the digital circuit synthesized by DC is 1.6m W,the total power consumption of the pre-simulation is 42.1m W.Finally,the final layout is obtained according to the overall circuit and the layout area is 4200×2300mm~2.The parasitic parameters are extracted and the post-simulation is performed.Compared with the post-simulation results without the floating node calibration scheme,the SNDR is increased by 14.77d B and the SFDR is increased by 14.33d B.The post-PVT simulation results of the SAR ADC calibrated with the floating node shows that the SFDR is above 104d B and the SNDR is above 92d B.For the SAR ADC using the floating node calibration scheme,adding transient noise and performing PVT simulation,the simulation results show that the SFDR is above 104d B and the SNDR is above 92d B.The simulated power consumption after the overall SAR ADC is 43.2m W plus the 1.6m W synthesized by DC.The overall power consumption is 44.8m W and its Schreier FOM(Figure of Merit)is 166.3dB.