Calibration And Implementation Of A High Resolution Successive Approximation Register Analog To Digital Converter

As an indispensable part of the bridge between nature and the digital world,analog-to-digital converter has been used in many kinds of electronic instrument and equipment.Research about it has never stopped in recent 30 years.People invented different structures of ADCs aiming to different applications.With the high development of communication technology,high speed and resolution ADCs are in short supply.Some people come up with an idea that to replace the traditional RF receiver with a large bandwidth ADC,which can digitalize the RF signal directly.It seems unbelievable before but very sensible and valuable now.In addition,some instrument such as medical devices demand high resolution ADC more than 12 bits.Because of the limitation of the process,it is hard to reach that high resolution.Many calibration methods have been proposed.Among them,the digital calibration is the most popular one.An outstanding analog circuit can't leave without digital calibration now,so research about digital calibration allows no delay.This thesis aims to implement a high resolution successive approximation register(SAR)ADC,and tries to construct a time-interleaved ADC based on it.Meanwhile,a large amount of research about the capacitor mismatch has done in this paper.Many kinds of calibration methods have been verified both in foreground and background aspect and they are combined together by innovation.Moreover,mismatch between channels in time-interleaved ADC has also been calibrated.At last,all of these calibration methods are verified in MATLAB.Analysis about SAR ADC is based on the three aspects below:(1)System structure.Summarizing the structure of DAC and comparator,it also lists the factors which affect the speed and accuracy of comparator and gives some techniques to optimize it.Bootstrapped sampling is necessary in high resolution SAR ADCs,so this paper also summarizes some mainstream bootstrapped switches.Moreover,in order to solve the settling of DAC,redundant capacitor is added to the main DAC.Introduction about the redundancy is described in detail in this paper,so does the logic part.(2)Calibration algorithm.This paper analyzes the error resources in SAR ADC in detail and proposes several calibration algorithms to calibrate capacitor mismatch.In MATLAB,a module of a 16-bit SAR ADC is used to verify this algorithm,and the ENOB is improved to 15 bit successfully.Meanwhile,some research about channel mismatch in time-interleaved ADC has done.Offset,gain error and timing skew between channels are also calibrated in MATLAB.(3)Circuits.Analog part includes the sample switch and comparator.In order to decrease the distortion as much as possible,the high performance bootstrapped switch is adopted.We use “pre-amplifier + latch” as the structure of comparator.Its speed is increased and power consumption is decreased after optimizing.In digital circuits,clock generator and DAC control logic are designed.Verilog is used to describe the control logic of capacitor switching,and the mismatch of every capacitor is calculated and stored in memory.The final modeling and simulation show that the calibration improves the ENOB of a 16-bit SAR ADC to above 15 bits.Moreover,according to circuit simulation,a 12-bit,50MS/s SAR ADC has been designed and its SFDR and SNDR are 85 d B and 69 d B respectively.Based on this ADC,a two channel time-interleaved ADC can reach a speed of 100MS/s,and its SFDR is 85 d B and ENOB is 11 bits.