Research And Design Of A 12-bit Successive Approximation Analog-to-Digital Converter With Calibration

Nowadays,since the superiority and maturity of digital signal processing,when doing analog signal disposal,designers usually convert the signal into digital signal at the first step.The performance of the converter will directly affect the accuracy of signal processing.Many kinds of ADCs are available by now,including pipelined ADCs,sigma-delta ADCs,SAR ADCs,etc.among them,SAR ADCs have medium resolution and speed,Small chip area and low power consumption are guaranteed by CMOS process.Moreover,multi-channel conversion is easy to achieve.As a balance of resolution,speed,cost and power,SAR ADCs are conventional in medical instruments,industry controlling,micro-processors' analog-to-digital interfaces and so on.This dissertation describes the design of a 12-bit SAR ADC,whose power is 5V and sample rate is 1MHz.Research work can be categorized into these parts: 1.Research and design of DAC which generate successive voltage.To make the chip area smaller and lower dynamic power consumption,segmented capacitive structure is adopted.2.Research and design of comparator.A double-tail comparator with two-stage pre-amplifier is competed,which has fast speed.3.Research method of calibrating capacitors' mismatch.Design a string DAC used in calibration.Through post-simulation,in the case which introduced capacitor mismatch,the ENOB of the ADC can be increased from 8.3 to 10.7.The calibration method can improve the precision of SAR ADC obviously.The main difficulty of this dissertation is calibration of the parameter of capacitance array.Different from most products which calibrate in digital doman,this design achieves the expected result by using analog-digital hybrid method.This change can simplify digital logic and consume less chip area when using specified process.