Research On Key Techniques Of High Efficiency CMOS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

With the rapid development of integrated circuits,the demands on emerging electronic devices with restraint energy budget such as wireless sensor networks,energy harvesting systems and battery powered mobile devices have been rapidly increased.With the aggressive device scaling in modern CMOS technology,and low-voltage and low-power market trends,traditional ADC could not meet above applications completely.As a mandatory block in the analog front end of such devices,it puts forward higher requirements for ADC with ultra-low power consumption and operating frequency.Compared with delta-sigma ADC or pipeline ADC,successive approximation register(SAR)ADC have excellent performance in power consumption and area.However,since the parameters such as speed,accuracy,area,and power consumption mainly depend on the process,it is difficult for the SAR ADC to make a good compromise among the above parameters.In order to solve this issue,the Pipelined SAR ADC,which combines pipeline ADCs and SAR ADC,has been proposed to achieve a good tradeoff in speed,accuracy and power consumption.The thesis introduces the working principle of SAR ADC,describes in detail the influence on the switching scheme and mismatch of capacitor array and analyzes the key circuits suitable for low speed and low power consumption applications.The thesis introduces the system structure,working principle and key circuit of medium and high speed,low power Pipelined SAR ADC,and discusses the influence of non-ideal factors including the mismatch of capacitance,the input imbalance of the comparator and so on.Based on theoretical analysis and research,several kinds of ultra-low power consumption of switching scheme of capacitor are depicted in detail and two kinds of ultra-low power ADC with different sampling rates are designed using SMIC 0.18 ?m CMOS technology.1.The ultra-low-power SAR ADC has been fabricated in 0.18 ?m 1.8 V CMOS process.The operating voltage,accuracy and sampling frequency are 0.3V,8-bit and 10 k S/s,respectively.On account of the presented sub-DAC merged switching scheme reducing the switch energy by 98.4% and capacitance value by 75% compared with conventional switching architecture,the energy consumption of the SAR ADC is decreased drastically.This thesis also introduces the influence of non-ideal factors on ADC and the design of low-voltage bootstrap switch,low-voltage two-stage dynamic comparator,low-leakage SAR control logic and so on.The measurement results show that effective number of bits(ENOB)of the ADC is 7.21 bit at the Nyquist input frequency and 0.3 V supply voltage,achieving a figure-of-merit(Fo M)of 8.9 f J/conversion-step.The chip area and power consumption are 0.084 mm2 and 13.2n W,respectively.2.This thesis presents a low-power 12-bit 50MS/s asynchronous rail-to-rail Pipelined SAR ADC,which fabricated in 180 nm 1.8 V CMOS process.Design optimization is performed to achieve low power and high performance.A novel highly linear,power efficient switching scheme for the 2nd stage SAR ADC is proposed.The ADC consists of a 6-bit coarse SAR ADC,a residue amplifier and a 7-bit fine SAR ADC.The circuit architecture,the choice of operational amplifier,the design of the comparator in Sub ADC,switching scheme of capacitor array,the bootstrap switch are introduced in detail.The ADC operates asynchronously in order to simplify the design and save power.The ADC achieves low-power,high-resolution and high-speed operation without calibration.The test results show that the signal-to-noise harmonic distortion ratio(SNDR)is 67.01 d B and the spurious-free dynamic range(SFDR)is 77.13 d B with a voltage swing of 1.8V and a sampling rate of 50MS/s.The differential linearity(DNL)is 0.536/-0.676 LSB and the integral nonlinearity(INL)is 0.959/-1.025 LSB.The ADC has an effective area of approximately 0.315 mm2 and consumes only 10.08 mW of power.