Research On High Speed Low Power Analog To Digital Converter Based Successive Approximation Register

With the fast development of the wireless communication systems and the portable test instruments,the requirements for speed and power consumption of analog to digital converters(ADCs)are becoming more and more stringent.Successive approximation register(SAR)ADC has inherent simple architecture,small area and low power consumption.Meanwhile,the scaling of the size of CMOS devices makes it possible to improve the speed of SAR ADC.Moreover,the mobile communication,internet of things and consumer electronics make much more requests to ADCs for high speed and low power.Therefore,the research of high speed low power ADC based SAR has a great significance to the area of high speed low power applications.The SAR ADC with single IP core is studied in detail.The key techniques for further reducing the power consumption and improving the conversion speed of SAR ADC are discussed.The main research contents of this thesis are as follows:1.The low power switch capacitor array of digital to analog converter(DAC)in SAR ADC is studied carefully and a low-power Vcm-based split capacitor array architecture is proposed.By splitting the most significant bit(MSB)capacitor into a binary weighted capacitor array and using the terminal capacitor combined with Vcm to generate the reference voltage for the last bit conversion,the number of unit capacitor required in the DAC capacitor array is reduced,and the average power consumption during charge or discharge procedure is also decreased.Compared with the conventional architecture,the number of unit capacitor and the average power consumption required in the Vcm-based split capacitor array architecture is reduced by 93.7%and 75%,respectively.Moreover,the settlement speed is improved by 25%and the output common mode voltage of DAC remains almost stable during the whole conversion.By using the proposed Vcm-based split capacitor array architecture,a 10-bit SAR ADC is designed in 90nm CMOS technology.The logic control module of SAR ADC is also optimized to shorten the loop delay leading to improve the speed of SAR ADC.The simulation result shows that the sample rate of this ADC is up to 150MS/s.The ENOB and the power consumption of ADC are 9.9 bit and 2.2m W,respectively.2.In order to further improve the speed of SAR ADC,the speed-improvement techniques used in DAC module is studied.The redundancy compensation technique used to reduce the settlement time of DAC is analyzed and a segmented DAC architecture based binary redundancy compensation and split capacitor technique is proposed.By using the redundancy compensation technique,the requirement of settlement accuracy is decreased resulting in shortening the settlement time;by using the split capacitor technique,the time constant of DAC is reduced leading to improving the speed of DAC.For a 12 bit SAR ADC,the total settlement time of DAC is reduced by 55%and the speed is increased 1 times compared with conventional one.Based on the proposed high speed DAC architecture,a 12-bit high speed SAR ADC is implemented in 0.18?m CMOS technology.The measurement results show that the speed of ADC is up to 100MS/s,SNDR is 59dB,and the power is 6.2mW.3.The mismatches in DAC capacitive array have effects on the linearity of DAC.Thus,mismatch calibration technique is studied and a digital self-calibration technique by reusing the lower-bits capacitor array is proposed.Before the normal conversion phase,the lower several bits capacitor array is reused to measure and estimate the mismatch errors in higher one.Then the error codes are stored.After the normal conversion phase,the error codes are added to the raw output codes to achieve the final outputs.In addition,a low offset comparator is required to achieve accurate error values of capacitor mismatch.The impacts of the additional imbalance capacitor in different stages on the performance of comparator are discussed.It is shown that the intentional load capacitor imbalance in the first stage is more appropriate for offset calibration.Based on this,an offset calibration circuit based load capacitor compensation is proposed.By using this method,the offset of comparator can be reduced within one LSB,which meet the requirement of ADC.Based on the digital self-calibration technique,a 12bit SAR ADC is implemented in 40nm CMOS technology.The calibration method is verified by circuit simulation.The simulation result shows that the proposed digital self-calibration technique effectively reduced the effect of capacitor mismatch on the performance of SAR ADC.4.An improved dual capacitive array DAC is proposed by the research of exiting low power dual capacitive array DAC.Compared with the conventional architecture,the power and area of improved dual capacitive array DAC are reduced by 99.3%and 71.9%,respectively.The two-stage dynamic comparator is also studied and an improved two-stage dynamic comparator is proposed.By adding a latch as the load of the first stage,the gain of the proposed comparator is increased resulting in further improving the speed of comparator.