Design Of High-speed Energy-efficient Successive-approximation Analog-to-digital Converter

The rapid development of wearable mobile device, infrared sensor and wireless sensor network puts forward higher requirements on the miniaturization of electronic systems, and analog to digital converter(ADC) is the essential part of the system, its performance directly affects the performance of the whole system. Successive approximation register analog to digital converter(SAR ADC) is widely used for a long time for its low power consumption, small size, moderate speed etc, its design technology is getting more and more attention.This paper firstly analyzes the common structure and working principle of ADC, and compares their respective advantages and disadvantages. At the same time, at the points of dynamic power consumption and nonlinear parameters INL/DNL, this paper analyzes and compares the existing capacitor arrays of the SAR ADC, on the basis of that, completes a 6-bit 120MS/s SAR ADC circuit design. By designing and modeling the sandwich-finger capacitance, completes a monotonic conversion capacitor array, resulting improve effectively the speed and power consumption of the ADC; Moreover by cascoding a biased MOS at the top of traditional dynamic comparator, improves effectively the linearity of the comparator, and simulates its resolution and delay; Finally designs the asynchronous circuit, realizing the asynchronous sequence, effectively improves the speed and power consumption of the ADC.By using the Cadence design for circuit design and simulation platform, completes the ADC layout and simulation, the simulation experimental shows that under the power supply voltage of1.8V, the proposed SAR ADC is 120 Msps, and when the input signal frequency is 1.3 MHz, its SNR is 36.9dB, SNDR is 35.8dB, SFDR is 48.4dB and ENOB is 5.66 bit, power consumption is2.43 mW, FOM is 0.41pJ/Con.step.