Research And Implementation Of Low - Power And High - Speed Successive Approximation Analog - To - Digital Converter With Bridge - Capacitance Array

Along with the development of manufacturing and designing technology, the expanding application areas of different topologies of analog to digital converters (ADC) have more overlaps. In a traditional design, pipelined ADC would be chosen for the application with several tens to low hundreds of MS/s and8-bit to10-bit resolutions. However, nowadays successive approximation register (SAR) is also qualified for the target and become more competitive for its advantage of high energy efficiency and the compatibility with the advanced process.This paper presents a10-bit80-MS/s SAR ADC suitable to be integrated in a System on a Chip (SoC). By using the top-plate-sample switching scheme and the split capacitive array structure, the total capacitance is dramatically reduced which leads to low power and high speed. Since split structure makes capacitive array highly sensitive to parasitic capacitance, a three-row layout method is applied to the layout design. To overcome the charge leakage in the nanometer process, a special input stage is proposed in the comparator. As80MS/s sampling rate for a10-bit SAR ADC results in around1GHz logic control clock, a tunable clock generator is implemented inside. The prototype was fabricated in65nm1P9M (one-poly-nine-metal) GP (General Purpose) CMOS technology. Measurement results show a peak signal-to-noise and distortion ratio (SINAD) of48.3dB and1.6mW total power consumption with a figure of merit (FOM) of94.8fJ/conversion-step.