Research On Key Technology Of Successive-Approximation-register Analog-to-Digital Converter (SAR ADC)

Analog-to-Digital Converter?ADC?as a bridge to convert analog signals into digital signals has always been the key technology in the biomedical signal processing system,so the improvement of ADC performance will optimize the entire mixed-signal circuits.Successive approximation?SAR?ADC is typical for low power consumption,medium speed,and medium accuracy ADCs.The SAR ADC circuit structure uses the mixed-signal circuits,which effectively reduces the use of analog devices,reduces the overall chip area,and reduces power consumption,so it is widely used in the biomedical sensor system.This paper proposes a subthreshold dynamic latch comparator that can be used for differential 12-bit successive approximation analog-to-digital converters.Compared with the traditional structure to overcome the weakness of increased delay time when the comparator working at low voltage.By researching the working characteristics of the pre-amplifier structure in the comparator,a capacitor-controlled pre-amplifier circuit is proposed to improve the accuracy of the proposed comparator to 4?V,to avoid the degradation of the overall resolution of the SAR ADC due to the limitation of the accuracy of the comparator.The sub-threshold dynamic latch comparator uses a low power supply voltage to achieve a power consumption of only 0.68?W,and the overall power consumption of the 12-bit SAR ADC is 8.68?W.Based on the traditional V_offset calibration method of the comparator,the method of dividing the reset period of the comparator can realize the calibration of the mismatch of the comparator without reducing the working speed of the comparator.The average value of the mismatch voltage of the comparator is reduced from-22.58?V to-3.2?V.Based on the TSMC 65nm CMOS technology,this article designs a low-power SAR ADC that operates at a supply voltage of 0.9 V and a 12-bit 1.8MS/s sampling rate.Under the Nyquist input condition,the signal-to-noise-and-distortion ratio?SNDR?of the SAR ADC is 73.52dB,the spurious-free dynamic range?SFDR?is 91.6dB,the effective number of bits?ENOB?is 11.92-bit,the figure of merit?FOM?is 1.25fJ/cov-step,and the power consumption is 8.68?W.