| In recent years,analog-to-digital converters have been widely used in communication,instrumentation,biomedicine,image sensing and other fields.With the development and progress of science and technology,more and more high requirements are put forward for the performance of ADC,such as speed,accuracy,area,power consumption.Successive approximation A/D converter（SAR ADC）compared to the pipeline and over sampling A/D converter type,on the speed and accuracy are better performance,also because of its working principle and structure is simple,low power consumption,the advantages of smaller,now with a larger share in the market,in instruments and meters,image processing,It is widely used in data signal collector.In this thesis,based on the demand of image sensor,a single-ended input SAR ADC is implemented by using pseudo-difference structure,which greatly reduces the requirement of the driving ability of the previous stage.In order to meet the speed requirements,asynchronous timing is adopted.In addition,in order to pursue a smaller layout area,the segmented capacitor array is also adopted.The sampling circuit adopts the new gate voltage bootstrapping technology,so that the voltage at both ends of the switch gate source is maintained as the power supply voltage,and the on-resistance(RON)of the switch is maintained as a constant value,which greatly improves the linearity of the sampling network.The comparator adopts the architecture of the combination of pre-amplifier and dynamic latch,and the DAC capacitor array adopts MIM capacitor with a unit capacitance value of6.25f F.The SAR ADC adopts true single phase clock（TSPC）D flip-flop.TSPC can be used in high speed situations and its structure is simple.The logic control module mainly produces the control signals required by each module,and its main function is to control the connection of the lower plate of the capacitor array.Based on Cadence software platforms,this paper adopts 0.18μm 1P4M CMOS process to design the SAR ADC as a whole.The simulation results show that when the sampling frequency is 20MHz,SAR ADC dynamic performance is SFDR=76.34d B,THD=-76.15d B,SNR=73.85d B,SINAD=71.84d B,and ENOB=11.64bit. |
