Research And Design Of Analog - To - Digital Converter For TD - LTE - Advanced Terminal

TD-LTE-Advanced (Time Division-Long Term Evolution-Advanced) is Chinese fourth generation wireless communication technology with independent intellectual property. It absorbed the kernel technology of TD-SCDMA, reflecting the lat,est independent innovation results of China’s communication industry in the field of broadband wireless mobile communication. The proposition of TD-LTE-Advanced, guaranteeing the core competiveness in4G wireless communication, safeguarding our national security, has a very important strategic significance and economic value.This paper presents a high speed high precision and low power SAR ADC for TD-LTE-Advanced communication terminal. This paper starts from system modeling analyzing and simulating to schematic design and simulating, layout and post layout simulating with parasite included, hardware implementation and chip test.To achieve high speed and low power design, successive approximation register ADC is proposed. To reduce the sampling capacitance and enhance speed, top capacitor sampling technology is adopted. Therefore only half capacitor is needed compared with traditional technology. To improve the linearity of the DAC, the least significant bits has4bits and the most significant bits has7bits since the parasitic capacitance in the LSBs would drop the SNDR severely. The effect of split capacitor and parasitic capacitance on the linearity of DAC is discussed in detail and the formulation is derived, a new solution is given with little hardware cost. A novel digital control logic is employed based on time division multiple access. Compared to conventional logic, the number of logical gates is reduced by half. A new calibration method is introduced to reduce dynamic comparator offset voltage. High power efficiency is achieved by eliminating pre-amplifiers.This SAR ADC is implemented in SMIC65nm1P8M Mixed-Signal CMOS process. The chip occupies an area of0.3×0.2mm2and consumes2.4mW. The ADC achieves a peak SNDR of72.7dB and a peak SFDR of84.5dB at a50-MS/s sampling rate.