A14-bit Successive Approximation Register Analog To Digital Converter

The conversion between analog signal and digital signal is completed byanalog-to-digital converter(ADC), which is an important part of the mixed-signalintegrated circuits and systems, has been widely used in portable devices, industrialcontrol and other fields. Due to its comprehensive advantages of simple structure,lower power consumption, and moderate conversion rate and low temperatureperformance, successive approximation analog-to-digital converter (SAR ADC) hasbeen the core module of the infrared detector cryogenic readout circuit. Because ofthe increasing demands for ADCs’ accuracy in imaging system and affection by thecapacitance matching accuracy at the chip manufacturing process, digital calibrationis necessary for the SAR ADC whose accuracy is more than12bit. In this paper, adesign of14-bit SAR ADC for planar array infrared detector readout circuit isproposed.The proposed system architecture, principle and evaluation is introduced in thispaper. Some non-ideality factors are analyzed and a digital calibration algorithmwhich can distinguish between the positive and negative error voltage is proposed.This work can be categorized into three parts:(1) Three-segmented structure isadopted in capacitor array for main DAC through only96unit capacitors, therefore,more chip area is saved. By the specific timing, calibration code is got to calibrate-5mV5mV voltage range and20uV compensation accuracy can be realized throughthe design of calibration DAC.(2) Two comparators topology is used to cooperatewith each other to improve the design SAR ADC calibration accuracy and conversionspeed. A20uV voltage difference can be effectively resolved by the comparator foracquiring the calibration code and a75uV voltage difference is distinguished within39ns by the comparator for data conversion.(3) Considering the capacitor matchingand good isolation, calibration code is obtained by calibration DAC accurately, thuseffectively improve the precision of the proposed ADC.After circuit design and pre-simulation, the layout design and post-simulation arecompleted in this paper. The proposed SAR ADC is designed in charted0.35um2P4M process, occupying2.332mm2.975mm. Post-simulation results show that theDNL and INL are-1~1.2LSB and-5.3~1.1LSB respectively, its SNDR is76.49dBand ENOB is12.4bit.