Research On ESD Protection Devices Based On 21nm Advanced Technology

With the development of integrated circuit technology to nodes below 28 nm,the performance of integrated circuits and the complexity of chips are increasing.The ESD protection of advanced integrated circuits has become very challenging.In addition,due to the exponential growth in the cost of new product development of today's microelectronic products,suppliers need to provide necessary ESD protection at the IC and circuit board level.The ESD pulse energy at the system level is huge,and the IC may not be able to withstand it,which requires the combination of IC protection and system protection.According to the narrow protection window under the nano process,this thesis studies the ESD anti latch up,and completes the flow chip verification on the 21 nm process.At the same time,an on-chip and off chip collaborative design method is proposed.The work of this thesis mainly focuses on the following aspects:(1)Firstly,this thesis briefly introduces the current situation of ESD protection in nano process,introduces the design basis of ESD protection,five ESD test models in engineering application and the test methods of ESD protection devices in detail.This thesis expounds the design method of ESD protection window in detail,and introduces the protection design of four common ESD protection devices,diode,BJT,MOSFET and SCR.At the same time,the ESD full chip protection scheme is briefly described,which is used for RC between power rail and ground?The protection design of clamp and the protection methods of 6 discharge modes.(2)The latch up problem of nano process is studied.ESD protection devices are designed based on 21 nm process,and four kinds of ESD protection devices with high maintenance voltage are verified.Two kinds of dcscr devices without hysteresis are introduced.The device mechanism,optimization scheme and actual test results are introduced.Two kinds of SCR devices with high maintenance voltage are introduced.The device mechanism,optimization scheme and actual test results,as well as the test results of the optimization of device size and structure are introduced.(3)Aiming at the collaborative design of on-chip and off-chip ESD protection,a design scheme using ADS software is proposed.Firstly,the characteristic parameters of on-chip and off-chip protective devices are collected through testing,and then the simulation modeling of pulse source,off-chip protective device TVs and on-chip protective device is carried out through software.Finally,the operation of the whole system is simulated by software to verify the rationality of collaborative design.