Research On Electrostatic Discharge And ESD Protection Devices

Electrostatic discharge（ESD） damage is one of major reliability issues in integrated circuits. Appropriate and effective ESD protection schemes have to be employed to prevent damages on the reliability of modern ICs. As microelectronics technology continues to shrink into nano-metric dimensions, the ESD protection challenges are exacerbated by the protection circuit effectiveness or ESD protection level, especiall y in highly susceptible advanced CMOS technologies.In this paper, the research on high voltage ESD protection devices are focused.NLDMOS（N-channel, lateral, double-diffused MOS） devices with three layout styles are investigated and fabricated in a 0.5-μm 18 V CDMOS（Complementary and Double Diffusion MOS） process. The square-t ype n LDMOS provides more than 30% and 25% higher current handling capability per area than the traditional finger-t ype and octagonal-type structures, respectivel y. Furthermore, the square-t ype structure exhibits the relatively higher robustness and lower leakage current characteristics. Two groups of SCR（Silicon Controlled Rectifier） ESD devices with particular layout parameters were fabricated in 0.5μm 5V/18 V CDMOS process, and investigated by a transmission line pulse test system, respectively. Experimental data shows that with increasing layout spacing from P+ implant in N well to N+ implant in P well; the holding voltages grow linearly, but the failure current per area decreases linearly. Using anal ysis and simulation results, two equations for the holding voltage and failure current were generalized properly. The simulations of one-way LDMOS-SCR ESD devices with various length of the drift region have be en achieved. I-V curves show that with the decreasing of the length of drift region, the failure current per area grows, but holding voltage decreas es. Furthermore, minority carrier concentration, current density and electrical field on the key points have been sampled and anal yzed during the simulations. It is clearl y demonstrated that the reduction of internal carrier transport mobility and the constant of the turn-on resistance result in this phenomenon. The experimental data is highly appeal to the simu lation results. Due to DDSCR device consists of two one-way SCR structures, the hold voltage decreases and the failure current per area grows with the increasing of the special region length of DDSCR device. In order to increase the failure current per area without reducing the holding voltage, a new structure of LDMOS-SCR ESD device called M-ESD device is proposed. The memristor of M-ESD device can usefully co-operate with other components to dissipate the energy of ESD surges. Without the enlarging of performance area and the dropping of the holding voltage, the failure current per area of M-ESD device increases sharply, and its discharge capacit y boosts. In order to obtain a memristor unit suitable for M-ESD devices, Mo Se2 nanorods were firstly synthesized by hydrothermal method. Then the electrodes were made by photolithography. Ag/Mo Se₂/Au structure device displays an excellent bipolar resistive switching behavior with lower operation voltage.The research on ESD protection varistors is described in the paper. Ceramics Pr_1-xCa_xMnO₃（x = 0.1） is proposed as a new additive for Zn O ceramic varistor to improve its stability against direct current（DC） accelerated aging stress. Pr_1-xCa_xMO₃ sample was prepared by solid-state reaction and its electrical and magnetic transport properties were studied by DC and alternating current（AC） methods in different fields. The experiment data suggest that the resistance of Pr_{1- x}Ca-xMn O₃ ceramics actually consists of the grain resistance and the grain boundary resistance.The grain boundary resistance is normally several orders greater than the grain resistance. Fitting by Arrhenius law, the barrier height of grain boundary is 145 me V which is well coincident with that from fitting the R-T data. A novel structure of ESD protection varistor is presented. The theoretical analysis have been achieved, and software simulations show that the maximum and the oscillation amplitude of new varistor ’s discharge current are significantly smaller than that of the original one’s. In order to obtain a memristor element suitable for the new structure varistor, Bi Mn O_3+δ nanorods were prepared by an improved hydrothermal process. Further, the electrodes were made by photolithography. The bipolar resistive switching behavior of Ag/Bi Mn O_3+δ/Ag device is steady, and the results indicate the OFF/ON-state resistance ratio is up to 10.This paper also describes my research on anti-static ESD damage materials. The cuprous sulfide（Cu₂S） film was prepared by electrochemical deposition. Further, an ion sputtering instrument was used to fabricate point shaped silver electrodes on the surface of Cu₂ S film or the copper substrate for measuring. The resistive switching behaviors of Ag/Cu₂S/Ag sandwich structures were observed. The device shows a reversible, high rati o RS effect. This property may be used for multifunctional design of anti-electrostatic clothing.