Research And Design Of ESD Protection Devices Based On SCR And LDMOS

With the continuous progress of semiconductor manufacturing technology,the physical size of chips is getting smaller and smaller,and Electrostatic discharge(ESD)has increasingly become one of the main reasons for the failure of semiconductor devices.At the same time,the continuous compression of the design window also makes ESD design more difficult.Therefore,for traditional ESD protective devices,optimizing their triggering and holding characteristics to meet the requirements of narrow ESD design window has become a research hotspot in the industryThe research direction of this paper is device-level on-chip ESD protection technology.It mainly involves the simulation research and optimization design of Silicon Controlled Rectifier(SCR),Dual Direction Silicon Controlled Rectifier(DDSCR),Lateral double diffused MOSFET(LDMOS)and its inherent defects.The focus of work includes: analysis and research of traditional ESD protective devices,SCR modeling analysis and simulation optimization research,DDSCR optimization research and tape-out testing,LDMOS operating characteristics analysis and simulation optimization design.The innovative achievements of this paper are as follows:(1)In order to solve the traditional LVTSCR latch-up effect,an Enhanced Embedded P High Holding LVTSCR(EP?HHVSCR)structure is proposed in this paper.By inserting a PSD/NSD active region,an additional recombination action is introduced in this structure.The emitter injection efficiency is reduced and the base area recombination action is enhanced through the P shallow well below NMOS,while the current gain of PNP and NPN is reduced to improve the holding voltage.The breakdown voltage of the reverse PN junction and the trigger voltage will be further reduced by the implanted P shallow well.The new EP?HHVSCR and the traditional LVTSCR were simulated by TCAD simulation.Verify the current and voltage(I-V)characteristics of the two structures.Simulation indicates that the holding voltage of the new EEP?HHVSCR device is increased from 1.7V to 5.7V,trigger voltage reduced from 7.9V to 7.6V.(2)In order to solve the problem of low holding voltage of traditional DDSCR,a high holding DDSCR structure named HHV?DDSCR is proposed in this paper.This structure increases the surface path resistance by implanting the active region of NSD.The carriers flowing from the emitter in both positive and negative directions will be absorb by the implanted PSD1,meanwhile the number of carriers in the injection well will be reduced,the holding voltage will be increased.The doping concentration on the side of the reverse PN junction will be increased by PSD2,as a result the trigger voltage will be reduced.The simulation results show that the trigger voltage of the new HHV?DDSCR device decreases from 25 V to 17.6V,and the holding voltage increases from 1.8V to 13.9V.The tape-out test results show that the device maintains a high working voltage of 22 V.Meanwhile,by increasing the size of the implanted active region,the surface path resistance can be increased,and the current flowing through the path device can be extended to make the conduction of the device more uniform.The robustness of the device is enhanced and the secondary failure current can also be increased from 1.5A to 1.75 A.(3)In order to solve the problem of aggravation of latch effect caused by Kirk effect,a high holding LDMOS structure named HHV?LDMOS is proposed in this paper.The structure is improved on the basis of NPN?LDMOS.The doped concentration in the transistor base region is increased through the implanted N-type well and P-type well,which effectively enhances the compound effect of the base region and increases the holding voltage.At the same time,the trigger voltage of the device is not reduced to meet the requirements of high trigger voltage in the high voltage field.The simulation results show that the trigger voltage of HHV?LDMOS is 45.1V,and the holding voltage is increased from 7.2V to 31 V,which enhances the latch-up resistance ability of the device.