Optimization Of ESD Protection Device Structure And Study On Novel Anti-Latch-up Mode

In recent years,with the development of the global semiconductor manufacturing technology,the high-performance digital or analog integrated circuits?IC?are achieved,therefore,a large numbers of novel smart electronic products have emerged.To ensure the quality of the product,every chip on the board is given a specific wafer-level ESD?Electrostatic Discharge?capability,and every interface of electronic product has been embedded the system-level ESD protection device.ESD technology is inevitable in wafer-level or system-level circuit design.However,ESD protection device in IC will be faced with transient-induced latch-up effect in power clamp application,especially in medium or high voltage situation.In order to solve the latch-up,the holding voltage?V_h?of the ESD device has to be improved to higher than normal operation voltage.But,owing to the high V_h,the ESD protection capability of the ESD device will be weakened because the failure current(I_t2)and clamping voltage(V_CL)have to be degraded.Over the years,the optimization of V_h,I_t2and V_CLare studied widely,and many valuable technologies are proposed as well.On the other hand,with the development of the high-speed interface,the parasitic junction capacitance?C_j?of the off-chip ESD protection device has became sensitive,which drives the development of low capacitance ESD devices.Except for the V_h,I_t2and V_CL,the C_jhas became an important research subject.This thesis focuses on the on-chip medium/high-voltage?MV/HV?and off-chip low-capacitance?LC?ESD device designs.Two new ESD structures,a new high holding current ESD anti-latch-up mode and a new LC ESD protection array with current equalization technique are proposed.The main innovations include the following aspects.?1?A new snapback-free silicon-controlled rectifier?SFSCR?.This device eliminates the emitter injection efficiency of the parasitic bipolar NPN transistor by cathode zener injection technique,while the shortest surface SCR path is blocked by introducing the surface floating layers,thus eliminating all snapback inner structures.Therefore,the SFSCR can be used for power protection without any risk.On the other hand,the increased V_hhas to lead to the degradation on I_t2.To mitigate I_t2degradation,a novel half-surrounded finger-shaped layout is designed.Finally,the ESD robustness of the SFSCR enhances 59%without snapback.?2?Novel high holding current anti-latch-up mode in input/output?I/O?applications.Because the impedance after latch-up in I/O ESD and power clamp ESD are different.By studying the load line of the protected circuits,a novel high holding current design mode including regression curve design concept is proposed,and a new double-snapback characteristic is developed for matching high holding current mode.Meanwhile,five key design elements of the double-snapback characteristic is concluded to guild the design.?3?New double-snapback NPN bipolar transistor?DSNPN?for high holding current mode anti-latch-up ESD protection.A new high dose N-type layer is fabricated on the surface of drift region.When the DSNPN is triggered by ESD pulse,the surface and the body will produce double-modulation,thus leading to double-snapback.By changing the relevant parameters,the double-snapback is proved be adjustable.The DSNPN will bypass the I/O load line by the first snapback(1^stsnapback)and get the low V_CLand high I_t2by the second snapback(2^ndsnapback).According to the experimental results,the DSNPN can restrain latch-up from 0.5 to 1 A output buffer circuit under15 V driver voltage.As an extension,a novel transient staircase pulse?TSP?test concept is proposed to test the ESD transient regression curve for latch-up evaluation.According to the simulation,the TSP waveform can detect the transient regression curve of ESD device and give a new reference for ESD test technology.?4?A new current equalization technique for low-capacitance ESD array?LCESDA?.Based on simplified lateral process and diode array framework,a low leakage current?<10 n A?is realized between any two pins.Meanwhile,a LCESDA is achieved by embedding an adjustable SCR into the key steering diode.Except for high-speed protection,the LCESDA can also provide a direct-current?DC?power source protection without any latch-up risk.During the normal operation,the LCESDA realizes common-mode capacitance of 0.35 p F and differential mode capacitance of less than 0.1 p F.According to the standard experiments,every pin of LCESDA passed IEC61000-4-2/-4-5 ESD/EOS tests and achieved a good V_CL.