Design Of High Holding Voltage ESD Protection Devices And Their Latch-up Immunity Investigations

Electrostatic discharge(ESD)has unnegligible influence on integrated circuits(ICs)and related electronic products.With the rapid development of Bipolar-CMOS-DMOS(BCD)process technology and the expanded application areas of high-voltage ICs,it has become a tough problem that the traditional ESD protection devices for low-and medium-voltage ICs cannot be directly transplanted to high-voltage ICs.Therefore,designing high performance ESD protection devices for high-voltage ICs has become a hot topic in the semiconductor industy.In this thesis,the working principles of high-voltage ESD protection devices are studied based on the high-voltage IC process.By following the ESD design rules,ESD protection devices with high holding voltage and latch-up immunity are designed and optimized by adjusting the layout or metal wiring.Meanwhile,the electrical characteristics of the designed devices are analyzed by simulations using Sentaurus.The ESD performance of the taped out devices is also verified by experimental tests.The major content of this thesis can be summarized as follows.Firstly,the ESD models,failure types and the transmission line pulse(TLP)testing method are briefly introduced.The Technology Computer Aided Design(TCAD)simulation software,as well as the simulation flows of device structures and electrical characteristics,is explained.The ESD protection principles of diode,metal oxide semiconductor(MOS),silicon controlled rectifier(SCR)and SCR embedded laterally diffused MOS(LDMOS-SCR)are studied.The internal physical mechanisms of these devices under the ESD stress are discussed through 3D TCAD simulations.Secondly,the working principle and ESD performance of the traditional LDMOS-SCR fabricated in a 0.35-?m BCD process are explored by 3D TCAD simulations and TLP tests.Two novel devices are proposed by adding an N+ type ring and a drift layer at the anode region of traditional LDMOS-SCR,respectively.The TLP testing results show that,compared to the traditional LDMOS-SCR,the holding voltage of the new LDMOS-SCR devices with a N+ ring or a drift layer at the anode increases from 2.75 V to 8.41 and 16.20 V,respectively.Moreover,the holding voltage can be continuously improved by increasing the channel length and the space between the floating N+ and the N+ under anode.Besides,a novel LDMOS-SCR device is designed by inserting a NBL layer and embedding a P-body layer into the traditional LDMOS-SCR to enhance the holding voltage and latch-up immunity.Its working mechanism and ESD characteristics are tentatively evaluated by TCAD simulations due to the tape-out period limitation.Thirdly,a modified dual-directional SCR(DDSCR)embedded with a PMOS is designed and fabricated in a 0.5-?m BCD process.The 3D TCAD simulations and TLP testing results indicate that the new device not only owns low trigger voltage and high holding voltage,but also has a smaller layout area compared to the traditional DDSCR,which can improve the ESD robustness per unit area.Moreover,by adjusting the N+ and P+ block numbers,it is demonstrated that the modified device with a smaller ratio of N+/P+ exhibits higher holding voltage and stronger latch-up resistance.This design method can be helpful for designing oroptimizing high-voltage ESD protection devices.Finally,in order to further increase the holding voltage and enhance the latch-up immunity,a novel DDSCR with embedded NMOS is proposed,whose ESD characteristics are preliminarily evaluated by analyzing its equivalent circuit and 3D TCAD simulations.