Research On ESD/EFT Protection Techniques Of ColdFire MCU Chip

With the deep sub-micro manufacturing technology and design technology becoming more mature, MCU has more functions and a trend towards low power, small size and high performance and so on. The small size chip and low cost application system must reduce the number of the ESD protection device against EMI, and this will greatly decrease the capabilities of chip anti-electromagnetic interfenence. EMC is a key factor of MCU reliability design, and becomes very necessary during MCU chip design. The research background of the dissertation is Freescale QiangXin (Tianjin) EMC lab R&D program-Reliability Design and Testing of MCU chip. This program has passed chip level and system level testing.Based on the whole architecture analysis of 32-bit ColdFire MCU chip, the dissertation mainly studies the principles, robust design techniques of RSD A/D converter and linear regulator. The ESD/EFT protection circuit design, ESD/EFT design theory & test and PADRING SPICE verification are discussed in details. According to the FA results of traditional ESD/EFT protection circuit, the whole chip ESD/EFT protection network can reject ESD/EFT transient signals by the proposed novel circuit and I/O layout optimization techniques. The research findings are widely used to Freescale MCU products.The creativity of the dissertation is as below: The robust design of high performance RSD A/D converter and linear regulator is proposed. RSD A/D converter allows differential signal input and single ended signal input, has the advantages of low power consumption(20mW), high resolution(12bit), high speed(1Ms/s) and small silicon area(0.42mm2), and linear regulator has a stable output voltage with the low ripple(10mV), high accuracy(2%) and low quiescent current(100μA). The novel ESD/EFT trigger circuit with good powered ESD performance (>8KV) is proposed, it is not only designed for slow transient signal (60ns~10μs), but also for fast transient signal (<60ns), however, the traditional ESD trigger circuit with a poor powered ESD performance (<6KV) only takes care of fast transient signal (<60ns). The methods of avoiding latch-up and increasing the snapback voltage of NMOS clamp are proposed. The large substrate current during EFT events decreases the snapback voltage(less than 6V at worst case) and causes the latch-up. The latch-up around SoC level and module level of MCU is improved, and the snapback voltage of NMOS clamp is up to 8V by the layout optimization techniques.