Research On ESD Protection Design And Latch-up Immunity Of Integrated Circuits

With the advancement of integrated circuit technology,CMOS integrated circuit technology continues to shrink in scale to package more transistors in the same area to improve operating speed and performance.Therefore,the gate oxide is also reduced to increase the current density of the transistor,which makes the integrated circuit chip more and more fragile,and the failure of electronic products caused by ESD electrostatic discharge is becoming more and more obvious,which seriously deteriorates the reliability of the chip.Therefore,the issue of ESD protection of integrated circuits has received more and more attention from the domestic and foreign industries and academia.More and more researchers in the industry and academia have invested in the field of integrated circuit ESD protection design for in-depth research.Thus,ESD protection has also become a new research focus in the semiconductor industry.The main research direction of this paper is the anti-latch-up research in ESD protection design.Firstly,the article introduces the relevant basic theories and design difficulties of ESD protection.Then,based on a variety of different processes and working voltages,the anti-latch-up design of ESD protection devices is completed,which meets the protection design requirements of related application fields.The main work and innovations of this paper are summarized as follows:(1)Aiming at the low holding voltage of LVTSCR commonly used in advanced technology,a MLVTSCR device with low trigger voltage and high holding voltage is proposed.By segmenting the N+ area across the LVTSCR and embedding the P+ area in it,the holding voltage of the MLVTSCR device can be effectively increased.Secondly,by introducing a PLVTSCR device into NLVTSCR,another new type of ILVTSCR is formed.By introducing a new current discharge path in the device,the holding voltage of ILVTSCR is increased.Finally,a new type of vertical bipolar junction transistor(BJT)triggered silicon controlled rectifier(VBTSCR)is proposed.With the help of vertical NPN transistors in the floating base area,the new silicon controlled rectifier(SCR)structure in the same layout can achieve lower trigger voltage and better clamping ability than the previous enhanced silicon controlled rectifier(EMLSCR).The above three new ESD devices are more suitable for low-voltage ESDprotection projects than traditional ESD protection devices.(2)A series of optimization work has been carried out for the commonly used MLSCR devices of medium and high voltage.First,a new type of high holding voltage silicon controlled rectifier(HHSCR)embedded with NMOSFET is proposed.The HHSCR is constructed by embedding a NMOSFET in the P-well of the modified lateral silicon controlled rectifier(MLSCR),which has a compact layout and can provide higher robustness in a smaller area.Secondly,in view of the problem that the failure current of MLSCR decreases with the increase of the holding voltage,an enhanced gate-controlled diode-triggered silicon controlled rectifier(EGDTSCR)is proposed,which has significantly improved holding voltage and failure current.By adding two gate-controlled diodes to the traditional MLSCR device,EGDTSCR can provide a higher holding voltage while effectively improving the ESD robustness of the device.Finally,for RS232 system-level ESD protection,an on-chip TVS is designed to protect the RS232 I/O port.The on-chip TVS is implemented by IHBSCR,which has high holding voltage and almost no snapback characteristics,and the holding current is much higher than the maximum I/O operating current.By embedding two p+/DNW/n+ diodes into the traditional bidirectional DMLSCR,with the help of auxiliary discharge of the surface P+/DNW/N+ diode path,HBSCR has extremely high holding voltage(almost no snapback)and sufficiently high robustness,which can prevent the latch-up problem more effectively.(3)Based on the common latch-up problems in the high-voltage BCD process,several new and improved structures are proposed to effectively improve the anti-latching ability of high-voltage ESD devices.First,for the low holding voltage of LMDOS-SCR,a new ESD protection device MLDMOS-SCR with P+ floating is proposed.By floating the anode P+ and inserting an additional P+ area at the source region,an RC circuit is formed to reduce the trigger and a floating PIN diode to increase the holding voltage.Secondly,an improved lateral double diffused MOS silicon controlled rectifier(ILDMOS-SCR)is proposed for the low holding voltage of LDMOS-SCR.By embedding a gate-controlled diode in the traditional LDMOS-SCR,with the aid of the auxiliary discharge of the reverse gate-controlled PIN diode path,the ILDMOS-SCR can greatly increase the holding voltage to achieve latch-up immunity.In addition,by increasing the device width,the current saturation effect in the ILDMOS-SCR single-finger device is effectively solved,and excellent ESDperformance is achieved.Finally,a SEG-LDMOS-DDSCR with high holding voltage is realized by using the segmentation technology.By segmenting the source N+ on both sides of the bidirectional LDMOS-DDSCR and embedding the P+ block into it,the emitter efficiency of the parasitic NPN is reduced and ? is declined.At the same time,the inserted P+ block forms an embedded PIN diode,which effectively improves the SEG-LDMOS-DDSCR.The high holding voltage of SEG-LDMOS-DDSCR avoids the latch-up effect that is common in high-voltage applications.