The Research Of Clock Tree Synthesis Methods Based On Chip Design Garfield5

The design methods of the integrated circuit meets more strict requirment according to thedevelopment of IC architecture and technology。As the IC architecture becomes more and morecomplicated and the frequency of clock keeps increasing,,the clock signal which is a universal timereference to synchronous digital circuit plays more and more important role in designs。Clock tree is atransmission network of clock signal,which is essential to the function and performance of system。In the phase of the back-end design of the intergrated circuit,CTS(Clock Tree Synthesis)isperformed to meet the static timing of the circuit。With the higher frequency and the more compicatedarchitecture of the clock,CTS become more and more important in the DSM(Deep Sub-Micron)back-enddesign。How to make the clock signal transmit and arrive at the registers at the same time,and how todecrease the amount of the inserted buffers and inverters(large number of buffers and inverters increasesthe power and area consumption)in the clock distribution network are the main point that must beconsidered in CTS。This thesis based on the design of Garfield5 SoC(System on Chip),using Astro and PrimeTimewhich are provided by Synopsys,discusses the flow of auto CTS and manual CTS optimization methods inthe DSM back-end design process。Astro integrates the function of floorplan,placement,clock treesynthesis and routing。The concept of the CTS is introduced at first as well as the related theory and someimportant elements that can affect the performance of the clock tree(such as clock source,clock period,clock tree latency,clock skew,transition time and the type of buffers )。Then the approachs to decrease theclock skew,adjust the clock delay and reduce the power consumption in the clock tree are discussed。Withthe design of Garfield5, under the SMIC 0.18um technology process, based on the Astro physical designprocess,the results of different design methods are analyzed.The experiment based on Garfield5 indicates:with the auto CTS flow using Astro,PowerManagement Control(PMC)module loaction optimization,adjusting the netweight of the wire and clocksource loaction can improve the CTS performance。It maintians the clock skew of CLK5M within 0.18 nsand the longest clock delay path less than 2 ns。The area of the Garfield5 chip is under the limit of 5mm×5mm andt highest frequency attains 100MHz。...