Research On The Design Method Of Clock Tree With High Frequency And Low Skew Of VLSI

With the increasing of chip scale,chip design becomes more and more complex,especially after the adoption of nanoscale technology,which brings many new challenges to improve circuit performance.The performance of the circuit depends on the frequency of the clock signal related to the data transmission and processing,which determines the working speed of the chip.Therefore,the design of distributed network of clock signals has become a key link in the design of digital integrated circuit,which affects the timing sequence convergence of the chip and directly affects the performance and function of the chip.A good clock network can satisfy the requirement of time series convergence even if the chip is in the worst case.Nowadays,the reduction of the characteristic process size and the increase of clock frequency make the design of VLSI more and more difficult,and the traditional clock tree synthesis is not easy to meet its high performance requirements for clock signals.This thesis is based on a very large scale SOC chip with very deep submicron(VDSM)process.For this complex VLSI,a hierarchical design scheme is adopted for the chip.The design of clock distribution network also presents multiple levels.For this reason,a hierarchical clock tree implementation scheme is proposed,and a script is written to feed back the global wiring resource information to the underlying modules considering the wiring requirements of the underlying modules.In order to obtain the low quality of clock skew clock network as a result,this article through screening,chose multi-source clock tree structure,the multi-source clock tree method is realized in the module level will module is divided into multiple clusters,and in each cluster to insert a clock buffer,of the same size to the output end of the root of these clocks as a new clock source clock tree synthesis.The number and distribution of clock root buffer have great influence on the clock quality of the module.For this reason,some heuristic methods are proposed to study the distribution position of clock root buffer in the module and the register controlled by each clock buffer.A)Adjust tap point position based on delay;B)Use kmeans algorithm for register allocation;C)Use bipartition algorithm for register allocation.The three methods have their own advantages,among which the bipartition algorithm for register allocation has the most obvious effect in reducing clock skew,with an average of 29% reduction in clock skew and a 7% reduction in clock delay.However,the disadvantage is that the power consumption increases by 20%.