The Optimization Of Multi-Level Clock Gate Design

With the development of chip industry process, the change of process and working environment have increasing influence up on the delay of instances and nets. In nanometer process, usually perform this as on-chip variation(OCV) in multi-mode multi-corner(MMMC) during sign-off. However, in VLSI design, the OCV leads to the uncertainty of clock because of the great latency on clock path. The timing becomes even harder to convergence. The best way to deal with this problem is increasing the percent of common path on clock.To reduce the power of chip, the usually way is inserting clock gates on clock path to close unnecessary working registers. The insertion of clock gates increases the branches and reduces the percent of common path on clock, which increases the bad influence of OCV on clock path.This paper performs several researches base on the design of YHFT-XX in 40 nanometer:First: Analysis the influences of OCV, MMMC and clock gate on clock path in nanometer process. For the success of sign-off, the STA with OCV and MMMC increase the uncertainty on clock, and the insertion of multi-level clock gates reduces the percent of common path on clock structure, which makes the timing constrain even harder to meet.Second: To decrease the clock skew in multi-level clock gate design and increase the common path on clock structure, this paper propose three algorithms to optimize the clock structure: collapse multi-level clock gates to one-level clock gates; merge the unnecessary logic gates which are inserted during the clock gates collaps; clone the clock gates which get big fan-out. After optimization, there is only one level clock gate left and the number of registers controlled by each clock gate is more even. The clock structure becomes simple, which proposes the possibility of increasing the common path.Third: Analysis several clock structures, and perform the mixed clock tree which make up of mesh and balance tree. This structure gets bigger percent of common path on clock, it can reduce the clock skew, and benefit for the timing convergence.Clock structure optimization apply on the core of YHFT-XX, and then implement clock tree synthesize, the clock skew has been reduce 21.7% and the slack has been reduce 19.7% when compare with the old clock structure. What's more, when implement the mixed clock tree after clock structure optimization, the clock skew has been reduce 39.3% and the slack has been reduce 12.6% compare with the normal clock tree synthesize after clock structure optimization. The clock structure mixed clock tree synthesize reduce the clock skew in multi-level clock gate design, and optimization and optimize the timing violation.