Physical Design And Implementation Of High Performance Chip Clock Tree

With the decrease of the feature size of semiconductor devices, especially in the nano phase, the physical design of the chip is faced with many challenges such as timing, low power consumption, and so on. Clock design and synthesis is the key to influence the timing of the convergence.This paper analyzes the background of the clock design in the current integrated circuit, and introduces the relevant theoretical knowledge of the clock tree synthesis and the reference flow of digital physical back end design. The structure of several clock networks that are often used in the design of a hybrid clock is studied. This method consists of the tree local and the top of the bottom layer of tree top two, the top of the tree H-tree through top to drive the mesh network, this method can be a large degree of deviation of the clock, the bottom tree local design uses clustering ideas, so that the clock path is relatively close, these two designs can effectively reduce the clock bias, and can reduce the impact of OCV on the clock. At last, the structure of the clock is realized in the 40nm process. The influence of the clock bias and OCV on the whole circuit is realized. The idea and algorithm of the whole circuit are introduced in this paper, and the process steps are analyzed in detail.The results show that using this clock structure, it can effectively reduce the clock bias and the impact of OCV on the design, the clock bias control within the 50ps, which reflects the superiority of the clock structure.